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Date:   Sat, 24 Sep 2022 15:29:30 +0700
From:   Bagas Sanjaya <bagasdotme@gmail.com>
To:     matthew.gerlach@linux.intel.com
Cc:     hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
        basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
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        linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
        tianfei.zhang@intel.com, corbet@lwn.net,
        gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
        jirislaby@kernel.org, geert+renesas@glider.be,
        andriy.shevchenko@linux.intel.com,
        niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
        macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for
 DFHv1
Message-ID: <Yy6/6nPa8buvqvbp@debian.me>
References: <20220923121745.129167-1-matthew.gerlach@linux.intel.com>
 <20220923121745.129167-2-matthew.gerlach@linux.intel.com>
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On Fri, Sep 23, 2022 at 05:17:40AM -0700, matthew.gerlach@linux.intel.com w=
rote:
> +With DFHv0, the register map of a given feature is located immediately f=
ollowing
> +the DFHv0 in the memory space.  With DFHv1, the location of the feature =
register
> +map can be specified as an offset to the DFHv1 or as an absolute address=
=2E  The DFHv1
> +structure is shown below:
> +
> +    +-------------------------------------------------------------------=
----+
> +    |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 =
ID 0|
> +    +-------------------------------------------------------------------=
----+
> +    |63                                 GUID_L                          =
   0|
> +    +-------------------------------------------------------------------=
----+
> +    |63                                 GUID_H                          =
   0|
> +    +-------------------------------------------------------------------=
----+
> +    |63                 Address/Offset                            1|  Re=
l  0|
> +    +-------------------------------------------------------------------=
----+
> +    |63 Size of register set  32|Params 31|30 Group    16|15 Instance   =
   0|
> +    +-------------------------------------------------------------------=
----+
> +    |63 Next parameter offset 32|31 Param Version 16|15 Param ID        =
   0|
> +    +-------------------------------------------------------------------=
----+
> +    |63                 Parameter Data                                  =
   0|
> +    +-------------------------------------------------------------------=
----+
> +
> +                                  ...
> +
> +    +-------------------------------------------------------------------=
----+
> +    |63 Next parameter offset 32|31 Param Version 16|15 Param ID        =
   0|
> +    +-------------------------------------------------------------------=
----+
> +    |63                 Parameter Data                                  =
   0|
> +    +-------------------------------------------------------------------=
----+
> +

For consistency with DFL location diagram (which is above the DFHv1
diagram above), use literal code block instead of table:

---- >8 ----

diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst
index 7c786b75b4988f..db6bff4aee25eb 100644
--- a/Documentation/fpga/dfl.rst
+++ b/Documentation/fpga/dfl.rst
@@ -584,7 +584,7 @@ across all types.
 With DFHv0, the register map of a given feature is located immediately fol=
lowing
 the DFHv0 in the memory space.  With DFHv1, the location of the feature re=
gister
 map can be specified as an offset to the DFHv1 or as an absolute address. =
 The DFHv1
-structure is shown below:
+structure is shown below::
=20
     +---------------------------------------------------------------------=
--+
     |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID=
 0|

Thanks.

--=20
An old man doll... just what I always wanted! - Clara

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