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From:   Liao Chang <liaochang1@huawei.com>
To:     <catalin.marinas@arm.com>, <will@kernel.org>, <guoren@kernel.org>,
        <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
        <aou@eecs.berkeley.edu>, <mhiramat@kernel.org>,
        <rostedt@goodmis.org>, <maz@kernel.org>,
        <alexandru.elisei@arm.com>, <liaochang1@huawei.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-csky@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>
Subject: [PATCH V4 0/3] kprobe: Optimize the performance of patching ss
Date:   Tue, 27 Sep 2022 10:24:32 +0800
Message-ID: <20220927022435.129965-1-liaochang1@huawei.com>
MIME-Version: 1.0
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Single-step slot would not be used until kprobe is enabled, that means
no race condition occurs on it under SMP, hence it is safe to pacth ss
slot without stopping machine.

v4:
1. Add Acked-by from Will Deacon
2. Mark Rutland provides some subtleties on arm64 micro-architecture
   that needs to follow.

v3:
1. Drop duplicated I-Cache maintenance for arm64.
2. Add Acked-by from Masami Hiramatsu.

v2:
Backport riscv patch to cksy and arm64.


Liao Chang (3):
  riscv/kprobe: Optimize the performance of patching single-step slot
  csky/kprobe: Optimize the performance of patching single-step slot
  arm64/kprobe: Optimize the performance of patching single-step slot

 arch/arm64/kernel/probes/kprobes.c | 27 +++++++++++++++++++++------
 arch/csky/kernel/probes/kprobes.c  |  6 +++++-
 arch/riscv/kernel/probes/kprobes.c |  8 +++++---
 3 files changed, 31 insertions(+), 10 deletions(-)

-- 
2.17.1