Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Conor Dooley <conor@kernel.org>
To:     Daire McNamara <daire.mcnamara@microchip.com>,
        Shravan Chippa <shravan.chippa@microchip.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor.dooley@microchip.com>
Cc:     Palmer Dabbelt <palmer@dabbelt.com>,
        Hugh Breslin <hugh.breslin@microchip.com>,
        devicetree@vger.kernel.org, Cyril Jean <Cyril.Jean@microchip.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Vattipalli Praveen <praveen.kumar@microchip.com>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        Albert Ou <aou@eecs.berkeley.edu>,
        Wolfgang Grandegger <wg@aries-embedded.de>,
        Lewis Hanly <lewis.hanly@microchip.com>
Subject: Re: [PATCH v6 00/11] New PolarFire SoC devkit devicetrees & 22.09 reference design updates
Date:   Tue, 27 Sep 2022 19:33:32 +0100
Message-Id: <166430333467.135094.14015061795483453798.b4-ty@microchip.com>
In-Reply-To: <20220927111922.3602838-1-conor.dooley@microchip.com>
References: <20220927111922.3602838-1-conor.dooley@microchip.com>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 8bit
Precedence: bulk

From: Conor Dooley <conor.dooley@microchip.com>

On Tue, 27 Sep 2022 12:19:12 +0100, Conor Dooley wrote:
> Resending with an extra patch making some more memory map changes that
> are to be introduced in the v2022.10 reference design. Since the
> v2022.10 and v2022.09 reference designs both indepedently break
> backwards compat, v2022.09 is not compatible with <= v2022.05 and
> v2022.10 is not compatible with v2022.09, I am doing the jump directly
> to v2022.10 rather than putting an intermediate step at v2022.09.
> 
> [...]

Applied to dt-for-next (in place of v5). As I pointed out earlier, I
will not make a PR for this until the reference design is available
on the PolarFire SoC GitHub.

[01/11] dt-bindings: riscv: microchip: document icicle reference design
        https://git.kernel.org/conor/c/a0d49a8f77f2
[02/11] dt-bindings: riscv: microchip: document the aries m100pfsevp
        https://git.kernel.org/conor/c/0ebdc51787db
[03/11] dt-bindings: riscv: microchip: document the sev kit
        https://git.kernel.org/conor/c/db3d481698ef
[04/11] riscv: dts: microchip: add pci dma ranges for the icicle kit
        https://git.kernel.org/conor/c/f890e67f292d
[05/11] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
        https://git.kernel.org/conor/c/99d451a7db16
[06/11] riscv: dts: microchip: icicle: update pci address properties
        https://git.kernel.org/conor/c/6fc655ed4986
[07/11] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses
        https://git.kernel.org/conor/c/ab291621a8b8
[08/11] riscv: dts: microchip: reduce the fic3 clock rate
        https://git.kernel.org/conor/c/fa52935abef4
[09/11] riscv: dts: microchip: add sevkit device tree
        https://git.kernel.org/conor/c/978a17d1a688
[10/11] riscv: dts: microchip: add a devicetree for aries' m100pfsevp
        https://git.kernel.org/conor/c/d49166646e44
[11/11] riscv: dts: microchip: update memory configuration for v2022.10
        https://git.kernel.org/conor/c/6c1193301791

Thanks,
Conor.