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From:   Biju Das <biju.das.jz@bp.renesas.com>
To:     Prabhakar <prabhakar.csengg@gmail.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>
CC:     Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [RFC PATCH 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD
 clocks support PM
Thread-Topic: [RFC PATCH 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD
 clocks support PM
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Date:   Wed, 28 Sep 2022 07:02:29 +0000
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 <20220927203044.751611-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Prabhakar,

> Subject: [RFC PATCH 1/2] clk: renesas: rzg2l: Don't assume all CPG_MOD
> clocks support PM
>=20
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>=20
> There are cases where not all CPG_MOD clocks should be assumed to
> support PM. For example on the CRU block there is a particular
> sequence that needs to be followed to initialize the CSI-2 D-PHY in
> which individual clocks need to be turned ON/OFF, due to which Runtime
> PM support wasn't used by the CRU CSI-2 driver.
>=20
> This patch adds support to allow indicating if PM is supported by the
> CPG_MOD clocks. A new macro is DEF_NO_PM() is added which sets the
> no_pm flag in struct rzg2l_mod_clk and when the driver uses Runtime PM
> support no_pm flag is checked to see if the clk needs to included as
> part of Runtime PM.
>=20
> CPG_MOD clocks with no_pm flag set need to be individually turned
> ON/OFF depending on the requirement of the driver.
>=20
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/clk/renesas/rzg2l-cpg.c | 35 +++++++++++++++++++++++++++++---
> -  drivers/clk/renesas/rzg2l-cpg.h | 12 ++++++++---
>  2 files changed, 40 insertions(+), 7 deletions(-)
>=20
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c
> b/drivers/clk/renesas/rzg2l-cpg.c index 3ff6ecd61756..d275324909e7
> 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -114,6 +114,8 @@ struct rzg2l_cpg_priv {
>  	struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;  };
>=20
> +static struct rzg2l_cpg_priv *rzg2l_cpg_priv;
> +
>  static void rzg2l_cpg_del_clk_provider(void *data)  {
>  	of_clk_del_provider(data);
> @@ -1223,18 +1225,42 @@ static int
> rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
>  	return devm_reset_controller_register(priv->dev, &priv->rcdev);
> }
>=20
> +static inline const struct rzg2l_mod_clk *rzg2l_get_mod_clk(const
> +struct rzg2l_cpg_info *info, int id) {
> +	unsigned int i;
> +
> +	id +=3D info->num_total_core_clks;
> +	for (i =3D 0; i < info->num_mod_clks; i++) {
> +		if (info->mod_clks[i].id =3D=3D id)
> +			return &info->mod_clks[i];
> +	}

May be as an optimization add ID and clk to a separate list
and traverse that smaller list for DEF_NO_PM case.

case CPG_MOD:
	return rzg2l_cpg_is_pm_mod(clkspec->args[1]);

Cheers,
Biju

> +
> +	return NULL;
> +}
> +
>  static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args
> *clkspec)  {
> +	struct rzg2l_cpg_priv *priv =3D rzg2l_cpg_priv;
> +	const struct rzg2l_cpg_info *info =3D priv->info;
> +	const struct rzg2l_mod_clk *mod_clk;
> +
>  	if (clkspec->args_count !=3D 2)
>  		return false;
>=20
> -	switch (clkspec->args[0]) {
> -	case CPG_MOD:
> -		return true;
> +	if (clkspec->args[0] !=3D CPG_MOD)
> +		return false;
>=20
> -	default:
> +	if (clkspec->args[1] >=3D info->num_hw_mod_clks) {
> +		dev_err(priv->dev, "Invalid clk index\n");
>  		return false;
>  	}
> +
> +	mod_clk =3D rzg2l_get_mod_clk(info, clkspec->args[1]);
> +	if (mod_clk && mod_clk->no_pm)
> +		return false;
> +
> +	return true;
>  }
>=20
>  static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused,
> struct device *dev) @@ -1348,6 +1374,7 @@ static int __init
> rzg2l_cpg_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->base))
>  		return PTR_ERR(priv->base);
>=20
> +	rzg2l_cpg_priv =3D priv;
>  	nclks =3D info->num_total_core_clks + info->num_hw_mod_clks;
>  	clks =3D devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
>  	if (!clks)
> diff --git a/drivers/clk/renesas/rzg2l-cpg.h
> b/drivers/clk/renesas/rzg2l-cpg.h index cecbdf5e4f93..1d68d3838392
> 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.h
> +++ b/drivers/clk/renesas/rzg2l-cpg.h
> @@ -176,6 +176,7 @@ enum clk_types {
>   * @off: register offset
>   * @bit: ON/MON bit
>   * @is_coupled: flag to indicate coupled clock
> + * @no_pm: flag to indicate if clock doesn't support PM
>   */
>  struct rzg2l_mod_clk {
>  	const char *name;
> @@ -184,9 +185,10 @@ struct rzg2l_mod_clk {
>  	u16 off;
>  	u8 bit;
>  	bool is_coupled;
> +	bool no_pm;
>  };
>=20
> -#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled)	\
> +#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled,
> _no_pm)	\
>  	{ \
>  		.name =3D _name, \
>  		.id =3D MOD_CLK_BASE + (_id), \
> @@ -194,13 +196,17 @@ struct rzg2l_mod_clk {
>  		.off =3D (_off), \
>  		.bit =3D (_bit), \
>  		.is_coupled =3D (_is_coupled), \
> +		.no_pm =3D (_no_pm), \
>  	}
>=20
>  #define DEF_MOD(_name, _id, _parent, _off, _bit)	\
> -	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
> +	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false, false)
>=20
>  #define DEF_COUPLED(_name, _id, _parent, _off, _bit)	\
> -	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true)
> +	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true, false)
> +
> +#define DEF_NO_PM(_name, _id, _parent, _off, _bit)	\
> +	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false, true)
>=20
>  /**
>   * struct rzg2l_reset - Reset definitions
> --
> 2.25.1