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From:   "Michael Williams (ATG)" <Michael.Williams@arm.com>
To:     Will Deacon <will@kernel.org>,
        Besar Wicaksono <bwicaksono@nvidia.com>
CC:     Suzuki Poulose <Suzuki.Poulose@arm.com>,
        Robin Murphy <Robin.Murphy@arm.com>,
        Catalin Marinas <Catalin.Marinas@arm.com>,
        Mark Rutland <Mark.Rutland@arm.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
        Sudeep Holla <Sudeep.Holla@arm.com>,
        Thanu Rangarajan <Thanu.Rangarajan@arm.com>,
        "treding@nvidia.com" <treding@nvidia.com>,
        "jonathanh@nvidia.com" <jonathanh@nvidia.com>,
        "vsethi@nvidia.com" <vsethi@nvidia.com>,
        "mathieu.poirier@linaro.org" <mathieu.poirier@linaro.org>,
        "mike.leach@linaro.org" <mike.leach@linaro.org>,
        "leo.yan@linaro.org" <leo.yan@linaro.org>
Subject: RE: [PATCH v4 1/2] perf: arm_cspmu: Add support for ARM CoreSight PMU
 driver
Thread-Topic: [PATCH v4 1/2] perf: arm_cspmu: Add support for ARM CoreSight
 PMU driver
Thread-Index: AQHYsAsiCzQrPgyEQ0K9q7o3XCKJDa3rtSeAgAkRkUA=
Date:   Wed, 28 Sep 2022 08:31:24 +0000
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Hi Will,

> -----Original Message-----
> From: Will Deacon <will@kernel.org>
> Sent: 22 September 2022 14:53
> To: Besar Wicaksono <bwicaksono@nvidia.com>
> Subject: Re: [PATCH v4 1/2] perf: arm_cspmu: Add support for ARM CoreSigh=
t
> PMU driver

[...]

> > +/* Check if PMU supports 64-bit single copy atomic. */ static inline
> > +bool supports_64bit_atomics(const struct arm_cspmu *cspmu) {
> > +	return CHECK_APMT_FLAG(cspmu->apmt_node->flags, ATOMIC, SUPP); }
>=20
> Is this just there because the architecture permits it, or are folks
> actually hanging these things off 32-bit MMIO buses on arm64 SoCs?

The CPU PMU is often exposed on the CoreSight APB bus (32-bit), and althoug=
h this driver wouldn't normally be used to access that PMU, I wouldn't rule=
 out similar legacy APB and AHB interfaces being used for other PMUs. A fur=
ther issue is that the CoreSight PMU model includes a number of 32-bit cont=
rol registers.

Since issue H.a there is an alternative 64-bit native PMU interface describ=
ed in the Arm ARM, which must support 64-bit atomic accesses. You might exp=
ect this to also appear in CoreSight PMU at some point soon. That would nee=
d some additional updates to this driver because all the registers are now =
64 bit, which changes some offsets.

Regards,
Mike.