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From:   Guillaume Ranquet <granquet@baylibre.com>
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References: <20220919-v1-0-4844816c9808@baylibre.com> <20220919-v1-14-4844816c9808@baylibre.com>
 <d1346dcf6b6906d153c13c086bf963dc89c5549b.camel@mediatek.com>
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Date:   Wed, 28 Sep 2022 05:23:43 -0700
Message-ID: <CABnWg9u5bJgfRqug3wFUOnFb3c7Fv_9YN2p8CXmhcnBrqa+pQA@mail.gmail.com>
Subject: Re: [PATCH v1 14/17] phy: mediatek: add support for phy-mtk-hdmi-mt8195
To:     Chunfeng Yun <chunfeng.yun@mediatek.com>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
        David Airlie <airlied@linux.ie>,
        Rob Herring <robh+dt@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Daniel Vetter <daniel@ffwll.ch>, CK Hu <ck.hu@mediatek.com>,
        Jitao shi <jitao.shi@mediatek.com>,
        Chun-Kuang Hu <chunkuang.hu@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>
Cc:     linux-mediatek@lists.infradead.org,
        dri-devel@lists.freedesktop.org,
        Pablo Sun <pablo.sun@mediatek.com>, linux-clk@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Mattijs Korpershoek <mkorpershoek@baylibre.com>,
        linux-arm-kernel@lists.infradead.org,
        linux-phy@lists.infradead.org, devicetree@vger.kernel.org
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On Wed, 28 Sep 2022 04:40, Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
>On Tue, 2022-09-27 at 06:23 -0700, Guillaume Ranquet wrote:
>> On Tue, 20 Sep 2022 09:46, Chunfeng Yun <chunfeng.yun@mediatek.com>
>> wrote:
>> > On Mon, 2022-09-19 at 18:56 +0200, Guillaume Ranquet wrote:
>> > > Add basic support for the mediatek hdmi phy on MT8195 SoC
>> > >
>> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
>> > >
>> > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>> > > b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>> > > index bb7593ea4c86..0157acdce56c 100644
>> > > --- a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>> > > +++ b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
>> > > @@ -1344,6 +1344,8 @@ static void mtk_hdmi_bridge_disable(struct
>> > > drm_bridge *bridge,
>> > >  	mtk_hdmi_disable_hdcp_encrypt(hdmi);
>> > >  	usleep_range(50000, 50050);
>> > >
>> > > +	phy_power_off(hdmi->phy);
>> > > +
>> > >  	hdmi->enabled = false;
>> > >  }
>> > >
>> > > diff --git a/drivers/phy/mediatek/Makefile
>> > > b/drivers/phy/mediatek/Makefile
>> > > index fb1f8edaffa7..c9a50395533e 100644
>> > > --- a/drivers/phy/mediatek/Makefile
>> > > +++ b/drivers/phy/mediatek/Makefile
>> > > @@ -12,6 +12,7 @@ obj-$(CONFIG_PHY_MTK_XSPHY)		+= phy-
>> > > mtk-
>> > > xsphy.o
>> > >  phy-mtk-hdmi-drv-y			:= phy-mtk-hdmi.o
>> > >  phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-
>> > > mt2701.o
>> > >  phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-
>> > > mt8173.o
>> > > +phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-
>> > > mt8195.o
>> > >  obj-$(CONFIG_PHY_MTK_HDMI)		+= phy-mtk-hdmi-drv.o
>> > >
>> > >  phy-mtk-mipi-dsi-drv-y			:= phy-mtk-mipi-dsi.o
>> > > diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
>> > > b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
>> > > new file mode 100644
>> > > index 000000000000..149015b64c02
>> > > --- /dev/null
>> > > +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
>> > > @@ -0,0 +1,673 @@
>> > > +// SPDX-License-Identifier: GPL-2.0
>> > > +/*
>> > > + * Copyright (c) 2021 MediaTek Inc.
>> > > + * Copyright (c) 2021 BayLibre, SAS
>> > > + */
>> > > +#include <linux/delay.h>
>> > > +#include <linux/io.h>
>> > > +#include <linux/mfd/syscon.h>
>> > > +#include <linux/module.h>
>> > > +#include <linux/phy/phy.h>
>> > > +#include <linux/platform_device.h>
>> > > +#include <linux/types.h>
>> > > +#include <linux/nvmem-consumer.h>
>> > > +
>> > > +#include "phy-mtk-hdmi.h"
>> > > +#include "phy-mtk-hdmi-mt8195.h"
>> > > +
>> > > +static void mtk_hdmi_ana_fifo_en(struct mtk_hdmi_phy *hdmi_phy)
>> > > +{
>> > > +	/* make data fifo writable for hdmi2.0 */
>> > > +	mtk_hdmi_phy_mask(hdmi_phy, HDMI_ANA_CTL,
>> > > REG_ANA_HDMI20_FIFO_EN,
>> > > +			  REG_ANA_HDMI20_FIFO_EN);
>> > > +}
>> > > +
>> > > +static void
>> > > +mtk_mt8195_phy_tmds_high_bit_clk_ratio(struct mtk_hdmi_phy
>> > > *hdmi_phy,
>> > > +				       bool enable)
>> > > +{
>> > > +	mtk_hdmi_ana_fifo_en(hdmi_phy);
>> > > +
>> > > +	/* HDMI 2.0 specification, 3.4Gbps <= TMDS Bit Rate <= 6G,
>> > > +	 * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10
>> > > +	 */
>> > > +	if (enable)
>> > > +		mtk_hdmi_phy_mask(hdmi_phy, HDMI20_CLK_CFG,
>> > > +				  0x2 << REG_TXC_DIV_SHIFT,
>> >
>> > Use FIELD_PREP() macro, then no need define REG_TXC_DIV_SHIFT
>> > anymore.
>> >
>>
>> Didn't know about FIELD_* macros, will use them for V2.
>>
>> Thx for the suggestion.
>Please use helpers defined in phy-mtk-io.h, the register access helpers
>of mtk_hdmi_phy_* are already removed in phy next branch.
>
>Thanks a lot
>
>
Hi,

Thank you for the headsup, I've seen the change landed in
next-20220927 on which I'm currently rebasing.


Thx,
Guillaume.