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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id n3-20020a5d4203000000b0022acb7195aesm4514561wrq.33.2022.09.28.08.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Sep 2022 08:31:24 -0700 (PDT) References: <20220805085716.5635-1-yu.tu@amlogic.com> <20220805085716.5635-4-yu.tu@amlogic.com> <1jiln0yzgj.fsf@starbuckisacylon.baylibre.com> <4e3cdd6b-5861-8a4f-1df7-af763f77bad5@amlogic.com> <1jsflftm1y.fsf@starbuckisacylon.baylibre.com> <0c7e6d90-2ce3-25ab-84b6-026ce8a238a8@amlogic.com> <1jtu5uz0ry.fsf@starbuckisacylon.baylibre.com> <9f9cf980-c0c6-d5c3-ced8-8ab50e392470@amlogic.com> <21e14cc1-6b34-e6b0-8da2-ad4b34dac149@amlogic.com> User-agent: mu4e 1.8.7; emacs 28.1 From: Jerome Brunet To: Yu Tu , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Neil Armstrong , Kevin Hilman , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Martin Blumenstingl Subject: Re: [PATCH V3 3/6] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Date: Wed, 28 Sep 2022 17:27:07 +0200 In-reply-to: <21e14cc1-6b34-e6b0-8da2-ad4b34dac149@amlogic.com> Message-ID: <1jy1u3zfas.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: base64 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DQpPbiBXZWQgMjEgU2VwIDIwMjIgYXQgMTY6NDAsIFl1IFR1IDx5dS50dUBhbWxvZ2ljLmNvbT4g d3JvdGU6DQoNCj4gSGkgSmVyb21l77yMDQo+DQo+IE9uIDIwMjIvOC8zMCAxNTozNywgWXUgVHUg d3JvdGU6DQo+PiBPbiAyMDIyLzgvMzAgMTQ6NDQsIEplcm9tZSBCcnVuZXQgd3JvdGU6DQo+Pj4g WyBFWFRFUk5BTCBFTUFJTCBdDQo+Pj4NCj4+Pg0KPj4+IE9uIFR1ZSAzMCBBdWcgMjAyMiBhdCAx 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