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Subject: Re: [PATCH] clk: sunxi-ng: h6: Fix default PLL GPU rate
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     mturquette@baylibre.com, r.stratiienko@gmail.com,
        linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
        Jernej Skrabec <jernej.skrabec@gmail.com>
To:     Jernej Skrabec <jernej.skrabec@gmail.com>, samuel@sholland.org,
        wens@csie.org
Date:   Wed, 28 Sep 2022 16:42:56 -0700
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Message-Id: <20220928234259.9E92FC433C1@smtp.kernel.org>
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Quoting Jernej Skrabec (2022-09-28 13:01:22)
> In commit 4167ac8a657e ("clk: sunxi-ng: sun50i: h6: Modify GPU clock
> configuration to support DFS") divider M0 was forced to be 1 in order to
> support DFS. However, that left N as it is, at high value of 36. On
> boards without devfreq enabled (all of them in kernel 6.0), this
> effectively sets GPU frequency to 864 MHz. This is about 100 MHz above
> maximum supported frequency.
>=20
> In order to fix this, let's set N to 18 (register value 17). That way
> default frequency of 432 MHz is preserved.
>=20
> Fixes: 4167ac8a657e ("clk: sunxi-ng: sun50i: h6: Modify GPU clock configu=
ration to support DFS")
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> ---

Applied to clk-fixes