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From:   Rahul Tanwar <rtanwar@maxlinear.com>
To:     Stephen Boyd <sboyd@kernel.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "mturquette@baylibre.com" <mturquette@baylibre.com>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        linux-lgm-soc <linux-lgm-soc@maxlinear.com>,
        Yi xin Zhu <yzhu@maxlinear.com>
Subject: Re: [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel
 based IO to regmap based IO
Thread-Topic: [PATCH RESEND v2 1/5] clk: mxl: Switch from direct readl/writel
 based IO to regmap based IO
Thread-Index: AQHYzkwBN81C1Ig0E0aREB0eQMfyQQ==
Date:   Thu, 29 Sep 2022 05:29:57 +0000
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References: <cover.1663827071.git.rtanwar@maxlinear.com>
 <4c56443ecd9041f102681ebf36b6854090ab82e3.1663827071.git.rtanwar@maxlinear.com>
 <20220929001416.6F090C433D6@smtp.kernel.org>
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Hi Stephen,=0A=0AThanks for review and response.=0A=0A=0AOn 29/9/2022 8:14 =
am, Stephen Boyd wrote:=0A> This email was sent from outside of MaxLinear.=
=0A>=20=0A>=20=0A> Quoting Rahul Tanwar (2022-09-21 23:24:24)=0A>> diff --g=
it a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c=0A>> ind=
ex 3179557b5f78..c83083affe88 100644=0A>> --- a/drivers/clk/x86/clk-cgu-pll=
.c=0A>> +++ b/drivers/clk/x86/clk-cgu-pll.c=0A>> @@ -1,8 +1,9 @@=0A>>   // =
SPDX-License-Identifier: GPL-2.0=0A>>   /*=0A>> + * Copyright (C) 2020-2022=
 MaxLinear, Inc.=0A>>    * Copyright (C) 2020 Intel Corporation.=0A>> - * Z=
hu YiXin <yixin.zhu@intel.com>=0A>> - * Rahul Tanwar <rahul.tanwar@intel.co=
m>=0A>> + * Zhu Yixin <yzhu@maxlinear.com>=0A>=20=0A> Does Zhu Yixin approv=
e? They're not Cced on this patch.=0A=0A=0AZhu Yixin is part of linux-lgm-s=
oc@maxlinear.com mail list which is CCed=20=0Ahere. In v3, i will separatel=
y CC Yixin and request him to review again=20=0Aand provide a Reviewed-by t=
ag if no concerns.=0A=0AThanks,=0ARahul=0A=0A>=20=0A>> + * Rahul Tanwar <rt=
anwar@maxlinear.com>=0A>>    */=0A>>=0A>>   #include <linux/clk-provider.h>=
=0A>=20=0A>=20=0A=0A