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From:   Rahul Tanwar <rtanwar@maxlinear.com>
To:     Stephen Boyd <sboyd@kernel.org>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "mturquette@baylibre.com" <mturquette@baylibre.com>
CC:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        linux-lgm-soc <linux-lgm-soc@maxlinear.com>
Subject: Re: [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow
 parent clock rate change
Thread-Topic: [PATCH RESEND v2 5/5] clk: mxl: Add a missing flag to allow
 parent clock rate change
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Date:   Thu, 29 Sep 2022 05:46:57 +0000
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On 29/9/2022 8:18 am, Stephen Boyd wrote:=0A> This email was sent from outs=
ide of MaxLinear.=0A>=20=0A>=20=0A> Quoting Rahul Tanwar (2022-09-21 23:24:=
28)=0A>> One of the clock entry "dcl" clk's rate can only be changed by=0A>=
> changing its parent's clock rate. But it was missing to have=0A>> CLK_SET=
_RATE_PARENT flag as enabled.=0A>>=0A>> Add/enable CLK_SET_RATE_PARENT flag=
 for dcl clk in order to=0A>> allow its clk rate to be changed via its pare=
nt's clk.=0A>>=0A>> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>=0A>=
> ---=0A>=20=0A> Any Fixes tag?=0A>=20=0A=0A=0AMissed it, will add in v3.=
=0A=0AThanks,=0ARahul=0A=0A=0A>=20=0A=0A