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Received: from PH7PR12MB5712.namprd12.prod.outlook.com (2603:10b6:510:1e3::13) by CH0PR12MB5234.namprd12.prod.outlook.com (2603:10b6:610:d1::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.20; Thu, 29 Sep 2022 07:01:26 +0000 Received: from PH7PR12MB5712.namprd12.prod.outlook.com ([fe80::aff2:40f5:fbfb:5f37]) by PH7PR12MB5712.namprd12.prod.outlook.com ([fe80::aff2:40f5:fbfb:5f37%5]) with mapi id 15.20.5654.014; Thu, 29 Sep 2022 07:01:26 +0000 Message-ID: <9c40ef91-b7fc-5ee6-2ab5-446a10f8c00a@amd.com> Date: Thu, 29 Sep 2022 12:31:13 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH 2/2] perf/x86/amd/lbr: adjust LBR regardless of filtering Content-Language: en-US To: Stephane Eranian Cc: linux-kernel@vger.kernel.org, peterz@infradead.org, ananth.narayan@amd.com, ravi.bangoria@amd.com References: <20220928184043.408364-1-eranian@google.com> <20220928184043.408364-3-eranian@google.com> From: Sandipan Das In-Reply-To: <20220928184043.408364-3-eranian@google.com> Content-Type: text/plain; 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Users of LBR usually expects > the from address to point to a branch instruction. The kernel has code to > adjust the from address via get_branch_type_fused(). However this correction > is only applied when a branch filter is applied. That means that if no > filter is present, the quality of the data is lower. > > Fix the problem by applying the adjustment regardless of the filter setting, > bringing the AMD LBR to the same level as other LBR implementations. > > Signed-off-by: Stephane Eranian > --- > arch/x86/events/amd/lbr.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c > index 2e1c1573efe7..38a75216c12c 100644 > --- a/arch/x86/events/amd/lbr.c > +++ b/arch/x86/events/amd/lbr.c > @@ -99,12 +99,13 @@ static void amd_pmu_lbr_filter(void) > struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > int br_sel = cpuc->br_sel, offset, type, i, j; > bool compress = false; > + bool fused_only = false; > u64 from, to; > > /* If sampling all branches, there is nothing to filter */ > if (((br_sel & X86_BR_ALL) == X86_BR_ALL) && > ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE)) > - return; > + fused_only = true; > > for (i = 0; i < cpuc->lbr_stack.nr; i++) { > from = cpuc->lbr_entries[i].from; > @@ -116,8 +117,11 @@ static void amd_pmu_lbr_filter(void) > * fusion where it points to an instruction preceding the > * actual branch > */ > - if (offset) > + if (offset) { > cpuc->lbr_entries[i].from += offset; > + if (fused_only) > + continue; > + } > > /* If type does not correspond, then discard */ > if (type == X86_BR_NONE || (br_sel & type) != type) { Reviewed-by: Sandipan Das