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Date:   Thu, 29 Sep 2022 05:44:18 -0400
Message-ID: <86ill67bwt.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Jianmin Lv <lvjianmin@loongson.cn>
Cc:     Thomas Gleixner <tglx@linutronix.de>, linux-kernel@vger.kernel.org,
        loongarch@lists.linux.dev, Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Huacai Chen <chenhuacai@loongson.cn>,
        Bjorn Helgaas <bhelgaas@google.com>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Len Brown <lenb@kernel.org>, linux-pci@vger.kernel.org,
        linux-acpi@vger.kernel.org
Subject: Re: [PATCH V1 1/2] irqchip/loongson-pch-pic: Support to set irq type for ACPI path
In-Reply-To: <71fc2d5b-fc3c-0a2d-65ce-df7d5bb26503@loongson.cn>
References: <1660615291-35409-1-git-send-email-lvjianmin@loongson.cn>
        <1660615291-35409-2-git-send-email-lvjianmin@loongson.cn>
        <86leq37duw.wl-maz@kernel.org>
        <71fc2d5b-fc3c-0a2d-65ce-df7d5bb26503@loongson.cn>
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On Wed, 28 Sep 2022 22:35:17 -0400,
Jianmin Lv <lvjianmin@loongson.cn> wrote:
>
> On 2022/9/28 =E4=B8=8B=E5=8D=8810:49, Marc Zyngier wrote:
> > On Mon, 15 Aug 2022 22:01:30 -0400,
> > Jianmin Lv <lvjianmin@loongson.cn> wrote:
> >>=20
> >> For ACPI path, the translate callback used IRQ_TYPE_NONE and ignored
> >> the irq type in fwspec->param[1]. For supporting to set type for
> >> irqs of the irqdomain, fwspec->param[1] should be used to get irq
> >> type.
> >>=20
> >> On Loongson platform, the irq trigger type of PCI devices is
> >> high level, so high level triggered type is inputed to acpi_register_g=
si
> >> when create irq mapping for PCI devices.
> >>=20
> >> Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
> >> ---
> >>   drivers/acpi/pci_irq.c                 |  3 ++-
> >>   drivers/irqchip/irq-loongson-pch-pic.c | 10 ++++++----
> >>   2 files changed, 8 insertions(+), 5 deletions(-)
> >=20
> > $ ./scripts/get_maintainer.pl drivers/acpi/pci_irq.c
> > Bjorn Helgaas <bhelgaas@google.com> (supporter:PCI SUBSYSTEM)
> > "Rafael J. Wysocki" <rafael@kernel.org> (supporter:ACPI)
> > Len Brown <lenb@kernel.org> (reviewer:ACPI)
> > linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM)
> > linux-acpi@vger.kernel.org (open list:ACPI)
> > linux-kernel@vger.kernel.org (open list)
> >=20
> > How about you start Cc-ing some of the relevant people?
> >=20
> Ok, thanks, I'll cc relevant people list here.
>=20
> >>=20
> >> diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
> >> index 08e1577..34483b3 100644
> >> --- a/drivers/acpi/pci_irq.c
> >> +++ b/drivers/acpi/pci_irq.c
> >> @@ -393,7 +393,8 @@ int acpi_pci_irq_enable(struct pci_dev *dev)
> >>   	 * controller and must therefore be considered active high
> >>   	 * as default.
> >>   	 */
> >> -	int polarity =3D acpi_irq_model =3D=3D ACPI_IRQ_MODEL_GIC ?
> >> +	int polarity =3D acpi_irq_model =3D=3D ACPI_IRQ_MODEL_GIC ||
> >> +		       acpi_irq_model =3D=3D ACPI_IRQ_MODEL_LPIC ?
> >>   				      ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW;
> >=20
> > The comment just above this only talks about ARM. Should it be
> > updated?=20
>=20
> Ok, I'll update the comment.
>=20
>=20
> > Is this a limitation of the underlying interrupt controller?
> >=20
> It's the limitation that pci interrupt source of LoongArch only sends
> high level trigger signal to interrupt controller(though, pci spec
> requires asserted low).

Right, so this is the opposite problem ARM has.

But is it *always* intended to be built like this? Or is it a one-off
for this generation of Loongarch systems, to be fixed at a later time?

>=20
>=20
> >>   	char *link =3D NULL;
> >>   	char link_desc[16];
> >> diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/=
irq-loongson-pch-pic.c
> >> index b6f1392..5067010 100644
> >> --- a/drivers/irqchip/irq-loongson-pch-pic.c
> >> +++ b/drivers/irqchip/irq-loongson-pch-pic.c
> >> @@ -177,13 +177,15 @@ static int pch_pic_domain_translate(struct irq_d=
omain *d,
> >>   	if (fwspec->param_count < 1)
> >>   		return -EINVAL;
> >>   -	if (of_node) {
> >> +	if (of_node)
> >>   		*hwirq =3D fwspec->param[0] + priv->ht_vec_base;
> >> -		*type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
> >> -	} else {
> >> +	else
> >>   		*hwirq =3D fwspec->param[0] - priv->gsi_base;
> >> +
> >> +	if (fwspec->param_count > 1)
> >> +		*type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
> >> +	else
> >>   		*type =3D IRQ_TYPE_NONE;
> >=20
> > Isn't that a change in behaviour if of_node is non-NULL and
> > param_count=3D=3D1?
> >=20
>=20
> It seems that current code here has bug that if fwspec->param_count=3D=3D1
> and of_node is non-null, fwspec->param[1] will be accessed, which is
> introduced from previous patch(irqchip/loongson-pch-pic: Add ACPI init
> support). Before the patch, for non-null of_node, translate
> callback(use irq_domain_translate_twocell) will return -EINVAL if
> fwspec->param_count < 2.
>=20
> For ACPI path, fwspec->param_count can be 1 or 2.
>=20
> So in this patch, I'll fix the bug and change the code as following:
>=20
>         if (fwspec->param_count < 1)
>                 return -EINVAL;
>=20
>         if (of_node) {
>                 if (fwspec->param_count < 2)
>                         return -EINVAL;
>=20
>                 *hwirq =3D fwspec->param[0] + priv->ht_vec_base;
>                 *type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
>         } else {
>                 *hwirq =3D fwspec->param[0] - priv->gsi_base;
>=20
>                 if (fwspec->param_count > 1)
>                         *type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
>                 else
>                         *type =3D IRQ_TYPE_NONE;
>         }
>
>=20
> >> -	}
> >>     	return 0;
> >>   }
> >=20
> > This irqchip change should probably be a separate patch.
> >=20
>=20
> As a separate patch, the input trigger type of pci devices will be low
> level because of lacking of workaround to acpi_pci_irq_enable, which
> will cause kernel hang, unless the patch of workaround to
> acpi_pci_irq_enable is in front of this separated patch.

That seems like a sensible requirement, but I really want to
understand whether PCI Loongarch will *always* generate INTx as
ACTIVE_HIGH or not. Because if that is ever going to change, we will
need a different way to inform the irqchip about the polarity
inversion.

	M.

--=20
Without deviation from the norm, progress is not possible.