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Message-ID: <17c5cc9c-50ea-aeac-04e0-20b6c093c7ec@collabora.com>
Date:   Thu, 29 Sep 2022 14:50:38 +0200
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Subject: Re: [PATCH v3] reset: mediatek: Move mediatek system clock reset to
 reset folder
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To:     Bo-Chen Chen <rex-bc.chen@mediatek.com>, sboyd@kernel.org,
        mturquette@baylibre.com, matthias.bgg@gmail.com,
        p.zabel@pengutronix.de
Cc:     runyang.chen@mediatek.com, miles.chen@mediatek.com,
        wenst@chromium.org, nfraprado@collabora.com,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org,
        Project_Global_Chrome_Upstream_Group@mediatek.com
References: <20220929121031.17523-1-rex-bc.chen@mediatek.com>
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
In-Reply-To: <20220929121031.17523-1-rex-bc.chen@mediatek.com>
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Precedence: bulk

Il 29/09/22 14:10, Bo-Chen Chen ha scritto:
> To manager mediatek system clock reset easier, we move the driver to
> drivers/reset.
> 
> The modifications in this series:
> - Move clk/mediatek/reset.c to reset/reset-mediatek-sysclk.c
> - Move reset data which are scattered around the mediatek drivers to
>    reset-mediatek-sysclk.c
> - For mtk clk drivers which support device, we can ues
>    mtk_reset_controller_register() to register reset controller using
>    auxiliary bus.
> - For mtk clk drivers which do not support device (only support
>    device_node), we use mtk_reset_{init/remove}_with_node to register
>    reset controller.
> 
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>

I've just analyzed this idea a bit more, and there's the outcome.

This driver would be fine, if some MediaTek SoCs weren't shipped with
a bootloader that supports only very small kernels... because then, if
the reset controller is not available at boot time, it's unlikely that
you can probe the eMMC or the uSD, so it won't be possible to actually
compile this driver as a module and load it afterwards.

Please don't misunderstand me: I like the idea of having the MediaTek
SoC sysclk reset controller as a ... reset controller driver but, to
make that work, one fundamental issue must be solved...

If the kernel is configured for, let's say, MT2701 and MT2712, we're
always building in reset controller support for MT7622, 7629, 8135, 8173,
8183, 8186, 8192, 8195 - and this list will grow with MT8188, and others.

Obviously, it's useless to have support for, say, MT7622, if the MT7622
system clock controllers aren't built-in, nor modules.

So, to make this idea to work, we have to find a way to:
1. Build in support only for the required SoC(s)
2. Put the reset index mapping arrays in SoC-specific files, or this
    single file driver will see an exponential growth.

Wrapping it up - as the driver is right now - we're losing flexibility:
we need to maintain the current flexibility while keeping the improvements
that are made with this proposal.

Ideas?

Regards,
Angelo

> ---
> Changes for v3:
> 1. Add reset bit of PCIE and USB for MT8195.
> 2. Rebased oo linux-next-0928.
> 
> Version for this series:
> v2 : https://lore.kernel.org/all/20220923045738.2027-1-rex-bc.chen@mediatek.com/
> v1 : https://lore.kernel.org/all/20220922141107.10203-1-rex-bc.chen@mediatek.com/
> RFC: https://lore.kernel.org/all/20220527090355.7354-1-rex-bc.chen@mediatek.com/