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Date:   Thu, 29 Sep 2022 18:59:24 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc:     Hal Feng <hal.feng@linux.starfivetech.com>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 00/30] Basic StarFive JH7110 RISC-V SoC support
Message-ID: <YzXc/FSbDpkElK0O@spud>
References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com>
 <4ddabe3a-9f55-2a6a-c1c1-ccc3fc74e98a@linaro.org>
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On Thu, Sep 29, 2022 at 04:45:26PM +0200, Krzysztof Kozlowski wrote:
> On 29/09/2022 16:31, Hal Feng wrote:
> 
> > This series is also available at 
> > https://github.com/hal-feng/linux/commits/visionfive2-minimal
> > 
> > [1] https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
> > [2] https://wiki.rvspace.org/
> > 
> > Emil Renner Berthing (17):
> >   dt-bindings: riscv: Add StarFive JH7110 bindings
> >   dt-bindings: timer: Add StarFive JH7110 clint
> >   dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> >   dt-bindings: sifive-l2-cache: Support StarFive JH71x0 SoCs
> >   soc: sifive: l2 cache: Convert to platform driver
> >   soc: sifive: l2 cache: Add StarFive JH71x0 support
> >   reset: starfive: jh7100: Use 32bit I/O on 32bit registers
> >   dt-bindings: reset: Add StarFive JH7110 reset definitions
> >   clk: starfive: Factor out common clock driver code
> >   dt-bindings: clock: Add StarFive JH7110 system clock definitions
> >   dt-bindings: clock: Add starfive,jh7110-clkgen-sys bindings
> >   clk: starfive: Add StarFive JH7110 system clock driver
> >   dt-bindings: clock: Add StarFive JH7110 always-on definitions
> >   dt-bindings: clock: Add starfive,jh7110-clkgen-aon bindings
> >   clk: starfive: Add StarFive JH7110 always-on clock driver
> >   RISC-V: Add initial StarFive JH7110 device tree
> >   RISC-V: Add StarFive JH7110 VisionFive2 board device tree
> 
> Where is the rest of patches? Lists got only 5 of them. Anyway this is a
> bit too big patchset. Split per subsystem.

They seem to be coming in over time in dribs and drabs. I assume it is
not a mailing list problem given how many lists are CCed on the mail and
the fact that they have different providers.

For v2 (or multiple v2s) please fix up your process so that this gets
sent normally and not a couple of patches every hour.

Thanks,
Conor.