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Date:   Fri, 30 Sep 2022 10:18:40 +0530
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Subject: Re: [PATCH v3 02/15] perf/x86/amd: Add IBS OP_DATA2 DataSrc bit
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To:     Namhyung Kim <namhyung@kernel.org>
Cc:     Peter Zijlstra <peterz@infradead.org>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Jiri Olsa <jolsa@kernel.org>,
        Stephane Eranian <eranian@google.com>,
        Ian Rogers <irogers@google.com>, Joe Mario <jmario@redhat.com>,
        Leo Yan <leo.yan@linaro.org>, alisaidi@amazon.com,
        Andi Kleen <ak@linux.intel.com>,
        Kan Liang <kan.liang@linux.intel.com>,
        dave.hansen@linux.intel.com, "H. Peter Anvin" <hpa@zytor.com>,
        Ingo Molnar <mingo@redhat.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Borislav Petkov <bp@alien8.de>, x86@kernel.org,
        linux-perf-users <linux-perf-users@vger.kernel.org>,
        linux-kernel <linux-kernel@vger.kernel.org>,
        Sandipan Das <sandipan.das@amd.com>, ananth.narayan@amd.com,
        Kim Phillips <kim.phillips@amd.com>, santosh.shukla@amd.com,
        Ravi Bangoria <ravi.bangoria@amd.com>
References: <20220928095805.596-1-ravi.bangoria@amd.com>
 <20220928095805.596-3-ravi.bangoria@amd.com>
 <CAM9d7cjVcGLn+dmajox6ASxx=YQYv9Viv+wzSXdaqCEJrow56w@mail.gmail.com>
From:   Ravi Bangoria <ravi.bangoria@amd.com>
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On 30-Sep-22 10:11 AM, Namhyung Kim wrote:
> Hi Ravi,
> 
> On Wed, Sep 28, 2022 at 2:59 AM Ravi Bangoria <ravi.bangoria@amd.com> wrote:
>>
>> IBS_OP_DATA2 DataSrc provides detail about location of the data
>> being accessed from by load ops. Define macros for legacy and
>> extended DataSrc values.
>>
>> Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
>> ---
>>  arch/x86/include/asm/amd-ibs.h | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/amd-ibs.h b/arch/x86/include/asm/amd-ibs.h
>> index f3eb098d63d4..cb2a5e113daa 100644
>> --- a/arch/x86/include/asm/amd-ibs.h
>> +++ b/arch/x86/include/asm/amd-ibs.h
>> @@ -6,6 +6,22 @@
>>
>>  #include <asm/msr-index.h>
>>
>> +/* IBS_OP_DATA2 DataSrc */
>> +#define IBS_DATA_SRC_LOC_CACHE                  2
>> +#define IBS_DATA_SRC_DRAM                       3
>> +#define IBS_DATA_SRC_REM_CACHE                  4
>> +#define IBS_DATA_SRC_IO                                 7
>> +
>> +/* IBS_OP_DATA2 DataSrc Extension */
>> +#define IBS_DATA_SRC_EXT_LOC_CACHE              1
>> +#define IBS_DATA_SRC_EXT_NEAR_CCX_CACHE                 2
>> +#define IBS_DATA_SRC_EXT_DRAM                   3
>> +#define IBS_DATA_SRC_EXT_FAR_CCX_CACHE          5
> 
> Is 4 undefined intentionally?

Yes, Here is the snippet from PPR (Processor Programming Reference) doc:

  Values | Description
  ---------------------------------------------------------------------
  0h     | No valid status.
  1h     | Local L3 or other L1/L2 in CCX.
  2h     | Another CCX cache in the same NUMA node.
  3h     | DRAM.
  4h     | Reserved.
  5h     | Another CCX cache in a different NUMA node.
  6h     | DRAM address map with "long latency" bit set.
  7h     | MMIO/Config/PCI/APIC.
  8h     | Extension Memory (S-Link, GenZ, etc - identified by the CS
         | target and/or address map at DF's choice).
  9h-Bh  | Reserved.
  Ch     | Peer Agent Memory.
  Dh-1Fh | Reserved.

Thanks,
Ravi