Received: by 2002:a05:6359:c8b:b0:c7:702f:21d4 with SMTP id go11csp3468298rwb; Fri, 30 Sep 2022 04:10:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM50c8f7l93JVcmE2imNa2zuXCWC1QH72Ms+Ssj0HPod9XoLe58/f2C4D/WdvWUD0/akvAVx X-Received: by 2002:a17:907:6e90:b0:782:a5ef:89a8 with SMTP id sh16-20020a1709076e9000b00782a5ef89a8mr6096265ejc.639.1664536231237; Fri, 30 Sep 2022 04:10:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664536231; cv=none; d=google.com; s=arc-20160816; b=07LLJpjUyR9RCLYVmG6zn8M7Nvtq+vU2Q0lygYKS212MPgwnQEjoGVP/nzes6aosAJ VgHVysESTVTM8rH5faRx6PCpYTRCOIXr097yTuz+uc5gv4KKdhpIuHbWFNC9VzvRXjBh mwP/C99sTkKxWNoNEvGKP+yqLd/ZuDrNNeCmzswuvI+Whno6UjvrIMgvHEaQfFetZN4Z Hix4zAs18I4TaYomoqQytEifbV8IAfmfNQUL6RoTiYo10qnTKeNHT0uLoEpy0k2MDs5d DHZf2Xbv+FuYPiaBq/V/YMX7dpY7kTmTwO438VJ/8Xpn9oAsJOZrrc7yfDz16Pm4Eg/i 5NKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0+J3lzFtGJuaZoo/NtlrYxYN343FiqZ+b+OlScrl97s=; b=o/YXRKH447P63/uAoXY7DLdwi3Yh3DXUUDsM5udN6G1zj/SD2yvJFMNKQXNuAbu2gf iVtkugveaaEYOVH8TAKnyJuaoczHWDWEXf6YcY+A9qSEHl/Lr/iAVgDCsWX3tM5cbWRF 8xBOotVH6hM6J+kOmsl/9mIBif3zaW/zbMz4z3NIV81t8nNIsSQWLzZ313dXhrDFzb9U CqCNsRsOiZldQiP5aNVctt5uq3jRhoYcdhsypqcWS5sxAc7YG4ptC6BPEU7gbW3Otzz2 gIQpFhqnLlXIvL4pQg/ygWNYGDeC/sOLkj/OWWFIroKvtHTNcxFSqBji/2Y8eEobrwT9 ER9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="ijXM0/WJ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g20-20020a056402321400b004587e08bbcbsi1263558eda.520.2022.09.30.04.10.05; Fri, 30 Sep 2022 04:10:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="ijXM0/WJ"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232633AbiI3K1B (ORCPT + 99 others); Fri, 30 Sep 2022 06:27:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231400AbiI3KXD (ORCPT ); Fri, 30 Sep 2022 06:23:03 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35485B853; Fri, 30 Sep 2022 03:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664533180; x=1696069180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yjeOmKxSHXyQaROUSIDgVbHM093jimLkUc7a+n1Knms=; b=ijXM0/WJKnoFOvt7i874MEPpXdYkM5MUBdV6lsOSaXnEHbOOURtUb7zS GThEdVG9TBmUDQyVHgnyH/rCgiYZgnfezyswue8znCVQSRYOJbe/6W63O OCUgMUb9eGrywZZ8Kv3jwHjTre0x+jfeBnpW1kdF/oMAbiYXf/RGCTBbL asTfoi5Z3l3y6ow8le+Pbw2J4WydARJu7mtDK3v5sVVH8F5ShCzbAe/za yex8rD4H7yJELchsk2gVMoXOy67iD946/LfVGDWui1uqJHzO2hoNMNAmS vqh2hHyxsH2CA4uvlwGb5nGy02N+RbbMhdL8sDSJhddU09LoffrBQgaV2 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10485"; a="328540170" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="328540170" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 03:19:07 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10485"; a="726807804" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="726807804" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 03:19:07 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar Subject: [PATCH v9 092/105] KVM: TDX: Handle TDX PV HLT hypercall Date: Fri, 30 Sep 2022 03:18:26 -0700 Message-Id: <1a481884ea0b0bf832c7d01977706692052245b4.1664530908.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Isaku Yamahata Wire up TDX PV HLT hypercall to the KVM backend function. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/tdx.c | 42 +++++++++++++++++++++++++++++++++++++++++- arch/x86/kvm/vmx/tdx.h | 3 +++ 2 files changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 16bee3b38bf4..73dba86f9341 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -520,7 +520,32 @@ void tdx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) bool tdx_protected_apic_has_interrupt(struct kvm_vcpu *vcpu) { - return pi_has_pending_interrupt(vcpu); + bool ret = pi_has_pending_interrupt(vcpu); + struct vcpu_tdx *tdx = to_tdx(vcpu); + + if (ret || vcpu->arch.mp_state != KVM_MP_STATE_HALTED) + return true; + + if (tdx->interrupt_disabled_hlt) + return false; + + /* + * This is for the case where the virtual interrupt is recognized, + * i.e. set in vmcs.RVI, between the STI and "HLT". KVM doesn't have + * access to RVI and the interrupt is no longer in the PID (because it + * was "recognized". It doesn't get delivered in the guest because the + * TDCALL completes before interrupts are enabled. + * + * TDX modules sets RVI while in an STI interrupt shadow. + * - TDExit(typically TDG.VP.VMCALL) from the guest to TDX module. + * The interrupt shadow at this point is gone. + * - It knows that there is an interrupt that can be delivered + * (RVI > PPR && EFLAGS.IF=1, the other conditions of 29.2.2 don't + * matter) + * - It forwards the TDExit nevertheless, to a clueless hypervisor that + * has no way to glean either RVI or PPR. + */ + return !!xchg(&tdx->buggy_hlt_workaround, 0); } void tdx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) @@ -822,6 +847,17 @@ static int tdx_emulate_cpuid(struct kvm_vcpu *vcpu) return 1; } +static int tdx_emulate_hlt(struct kvm_vcpu *vcpu) +{ + struct vcpu_tdx *tdx = to_tdx(vcpu); + + /* See tdx_protected_apic_has_interrupt() to avoid heavy seamcall */ + tdx->interrupt_disabled_hlt = tdvmcall_a0_read(vcpu); + + tdvmcall_set_return_code(vcpu, TDG_VP_VMCALL_SUCCESS); + return kvm_emulate_halt_noskip(vcpu); +} + static int handle_tdvmcall(struct kvm_vcpu *vcpu) { if (tdvmcall_exit_type(vcpu)) @@ -830,6 +866,8 @@ static int handle_tdvmcall(struct kvm_vcpu *vcpu) switch (tdvmcall_leaf(vcpu)) { case EXIT_REASON_CPUID: return tdx_emulate_cpuid(vcpu); + case EXIT_REASON_HLT: + return tdx_emulate_hlt(vcpu); default: break; } @@ -1135,6 +1173,8 @@ void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode, struct kvm_vcpu *vcpu = apic->vcpu; struct vcpu_tdx *tdx = to_tdx(vcpu); + /* See comment in tdx_protected_apic_has_interrupt(). */ + tdx->buggy_hlt_workaround = 1; /* TDX supports only posted interrupt. No lapic emulation. */ __vmx_deliver_posted_interrupt(vcpu, &tdx->pi_desc, vector); } diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h index ce2f49e15243..e79bdf01ad3e 100644 --- a/arch/x86/kvm/vmx/tdx.h +++ b/arch/x86/kvm/vmx/tdx.h @@ -113,6 +113,9 @@ struct vcpu_tdx { bool host_state_need_restore; u64 msr_host_kernel_gs_base; + bool interrupt_disabled_hlt; + unsigned int buggy_hlt_workaround; + /* * Dummy to make pmu_intel not corrupt memory. * TODO: Support PMU for TDX. Future work. -- 2.25.1