Received: by 2002:a05:6359:c8b:b0:c7:702f:21d4 with SMTP id go11csp3781511rwb; Fri, 30 Sep 2022 08:14:21 -0700 (PDT) X-Google-Smtp-Source: AMsMyM54ZUjCDSIOCbs2kaHWX48IQZXziv27bKqdb/5t2jGRgujejMmOjzNbaQKnk5TO8EEUe2Et X-Received: by 2002:a17:907:75e7:b0:77a:2378:91bb with SMTP id jz7-20020a17090775e700b0077a237891bbmr6835261ejc.329.1664550861555; Fri, 30 Sep 2022 08:14:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1664550861; cv=none; d=google.com; s=arc-20160816; b=u+fUa6OB81xnty8b/zU+0be9bJcaohbBU4iFsMow/dAQwvM7fHAf8w1eOECKW1Owup lWRhktAUlSfVB9Eoc/2aX+Au82n6bpy8SCErmRDUqijDmDmNDltS/5lnEVhv2hxaOBjv pPUmHT1VHLUpcxtypN3DNiK5UFILCjyhFh7WBslgiGisjwsi1tS9AcFLMsCih20e2QOo 1jekkJd1q8LTVWIZGbMQ/oTZlKeugllaSDdTUcq+y0MjE1ERJDduc6HbmDxihcpbOSuN 4YcUYG1hhbNabGNqvcmD0UP81FYSJrAe8lboHskvBeNCzTdERsYMPSLNGMRKKslCrXZk w8vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ohgAtFrtxJD/HigAL7+8dMtwCTZPADL2gZinlKi9QhU=; b=v9374CcIhkJiroEnNQqAPVdaPAgX/WR/vGmCBAObJLTKIcMtcOaNwxnm6SsedriCE6 1tTRPjon4IOqh/rlkJhHh4ZKLppYinA1dGMpetWBah13YrSqNj0gkVMhSXSJb5kXstuJ JF0JbiNun+mpuhDL2nntwIPpa8pazZksmDc9VxR0GESue6J1U6elJiWi2vbKO4zWjhg3 eedw+w2Qe6UZS/ADm6HilqxoIkokHd1hESi79X88lttRVdpa/p6IeZjSuE3hiDJMdcW8 wYLiZIv7LimOksWDfpALTJBfA8AXPBPY6aYU0hb1CwCDNqthTFKOrdUxg+VYELlx2W30 3xKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=N1Qs3Rk4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id b14-20020a056402278e00b00453d01c0d31si2483368ede.366.2022.09.30.08.13.55; Fri, 30 Sep 2022 08:14:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=N1Qs3Rk4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231795AbiI3OtE (ORCPT + 99 others); Fri, 30 Sep 2022 10:49:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231465AbiI3OsW (ORCPT ); Fri, 30 Sep 2022 10:48:22 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48D3112C1DB for ; Fri, 30 Sep 2022 07:48:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664549300; x=1696085300; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iE10WIJBtJTsaFxcXeBHtPpZOupPZSn9pP2DnyL7oJw=; b=N1Qs3Rk4dJ6CdAtLPRGHy8N1wnZL5c253HwNt+zHfAAZYqlN5Rpo937L 0vOnDhxJVuE6v+fmdzxPKMqT9aMtwCu43tSknoRvjXdDosVne2kh3nwJA KYppfvaTxOGwbxF3QbTRF891GE7fzyiMTeOmNQl42VDX49OrgRA3gq4di mKcdEY1PnrOHANjDoihXZQt0jDXRzrWg1NAkwKGWnpygoldGfnujFTjrB zARFnTtX0DifMgzI66nszYv1sBDCIO6vwO/dWzeeaiQelsoGBHZeQe+pd fE2c00v0ciJ6K/NCkwVVA0TTaOYVPgAHeAuuWVqKpbMl9UNOhPhEwMuIw g==; X-IronPort-AV: E=McAfee;i="6500,9779,10486"; a="328590069" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="328590069" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 07:48:15 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10486"; a="691271800" X-IronPort-AV: E=Sophos;i="5.93,358,1654585200"; d="scan'208";a="691271800" Received: from herrerop-mobl1.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.38.128]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 07:48:11 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 6DD3E104D61; Fri, 30 Sep 2022 17:48:02 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv9 07/14] x86/mm: Provide arch_prctl() interface for LAM Date: Fri, 30 Sep 2022 17:47:51 +0300 Message-Id: <20220930144758.30232-8-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930144758.30232-1-kirill.shutemov@linux.intel.com> References: <20220930144758.30232-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a couple of arch_prctl() handles: - ARCH_ENABLE_TAGGED_ADDR enabled LAM. The argument is required number of tag bits. It is rounded up to the nearest LAM mode that can provide it. For now only LAM_U57 is supported, with 6 tag bits. - ARCH_GET_UNTAG_MASK returns untag mask. It can indicates where tag bits located in the address. - ARCH_GET_MAX_TAG_BITS returns the maximum tag bits user can request. Zero if LAM is not supported. Signed-off-by: Kirill A. Shutemov Tested-by: Alexander Potapenko Reviewed-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/uapi/asm/prctl.h | 4 ++ arch/x86/kernel/process_64.c | 65 ++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/uapi/asm/prctl.h b/arch/x86/include/uapi/asm/prctl.h index 500b96e71f18..a31e27b95b19 100644 --- a/arch/x86/include/uapi/asm/prctl.h +++ b/arch/x86/include/uapi/asm/prctl.h @@ -20,4 +20,8 @@ #define ARCH_MAP_VDSO_32 0x2002 #define ARCH_MAP_VDSO_64 0x2003 +#define ARCH_GET_UNTAG_MASK 0x4001 +#define ARCH_ENABLE_TAGGED_ADDR 0x4002 +#define ARCH_GET_MAX_TAG_BITS 0x4003 + #endif /* _ASM_X86_PRCTL_H */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 1962008fe743..d75252a5c7be 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -742,6 +742,60 @@ static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr) } #endif +static void enable_lam_func(void *mm) +{ + struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); + unsigned long lam_mask; + unsigned long cr3; + + if (loaded_mm != mm) + return; + + lam_mask = READ_ONCE(loaded_mm->context.lam_cr3_mask); + + /* Update CR3 to get LAM active on the CPU */ + cr3 = __read_cr3(); + cr3 &= ~(X86_CR3_LAM_U48 | X86_CR3_LAM_U57); + cr3 |= lam_mask; + write_cr3(cr3); + set_tlbstate_cr3_lam_mask(lam_mask); +} + +#define LAM_U57_BITS 6 + +static int prctl_enable_tagged_addr(struct mm_struct *mm, unsigned long nr_bits) +{ + int ret = 0; + + if (!cpu_feature_enabled(X86_FEATURE_LAM)) + return -ENODEV; + + if (mmap_write_lock_killable(mm)) + return -EINTR; + + /* Already enabled? */ + if (mm->context.lam_cr3_mask) { + ret = -EBUSY; + goto out; + } + + if (!nr_bits) { + ret = -EINVAL; + goto out; + } else if (nr_bits <= LAM_U57_BITS) { + mm->context.lam_cr3_mask = X86_CR3_LAM_U57; + mm->context.untag_mask = ~GENMASK(62, 57); + } else { + ret = -EINVAL; + goto out; + } + + on_each_cpu_mask(mm_cpumask(mm), enable_lam_func, mm, true); +out: + mmap_write_unlock(mm); + return ret; +} + long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2) { int ret = 0; @@ -829,7 +883,16 @@ long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2) case ARCH_MAP_VDSO_64: return prctl_map_vdso(&vdso_image_64, arg2); #endif - + case ARCH_GET_UNTAG_MASK: + return put_user(task->mm->context.untag_mask, + (unsigned long __user *)arg2); + case ARCH_ENABLE_TAGGED_ADDR: + return prctl_enable_tagged_addr(task->mm, arg2); + case ARCH_GET_MAX_TAG_BITS: + if (!cpu_feature_enabled(X86_FEATURE_LAM)) + return put_user(0, (unsigned long __user *)arg2); + else + return put_user(LAM_U57_BITS, (unsigned long __user *)arg2); default: ret = -EINVAL; break; -- 2.35.1