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From:   Vidya Sagar <vidyas@nvidia.com>
To:     <bhelgaas@google.com>, <robh+dt@kernel.org>,
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        <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
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Subject: [PATCH V1 4/4] PCI: tegra194: Enable GPIO based Hot-Plug support
Date:   Sat, 1 Oct 2022 00:57:47 +0530
Message-ID: <20220930192747.21471-5-vidyas@nvidia.com>
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Enable the Hot-Plug functionality by registering it with the GPIO Hot-Plug
controller framework.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 64 ++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 0370e881422d..1b70aba08473 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -36,6 +36,7 @@
 #include <soc/tegra/bpmp.h>
 #include <soc/tegra/bpmp-abi.h>
 #include "../../pci.h"
+#include "../../hotplug/gpiophp.h"
 
 #define TEGRA194_DWC_IP_VER			0x490A
 #define TEGRA234_DWC_IP_VER			0x562A
@@ -281,6 +282,7 @@ struct tegra_pcie_dw {
 	struct phy **phys;
 
 	bool slot_pluggable;
+	struct gpio_hotplug_slot hp_slot;
 
 	struct dentry *debugfs;
 
@@ -296,6 +298,11 @@ static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
 	return container_of(pci, struct tegra_pcie_dw, pci);
 }
 
+static inline struct tegra_pcie_dw *to_tegra_pcie_from_slot(struct gpio_hotplug_slot *slot)
+{
+	return container_of(slot, struct tegra_pcie_dw, hp_slot);
+}
+
 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
 			       const u32 reg)
 {
@@ -1046,6 +1053,45 @@ static const struct dw_pcie_ops tegra_dw_pcie_ops = {
 	.stop_link = tegra_pcie_dw_stop_link,
 };
 
+static int tegra_pcie_slot_enable(struct gpio_hotplug_slot *slot)
+{
+	struct tegra_pcie_dw *pcie = to_tegra_pcie_from_slot(slot);
+	int ret;
+
+	ret = tegra_pcie_dw_start_link(&pcie->pci);
+	if (!ret)
+		pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
+
+	return ret;
+}
+
+static int tegra_pcie_slot_disable(struct gpio_hotplug_slot *slot)
+{
+	struct tegra_pcie_dw *pcie = to_tegra_pcie_from_slot(slot);
+	u32 val;
+
+	val = appl_readl(pcie, APPL_PINMUX);
+	val &= ~APPL_PINMUX_PEX_RST;
+	appl_writel(pcie, val, APPL_PINMUX);
+
+	/*
+	 * Deassert LTSSM state to stop the state toggling between
+	 * polling and detect.
+	 */
+	val = readl(pcie->appl_base + APPL_CTRL);
+	val &= ~APPL_CTRL_LTSSM_EN;
+	writel(val, pcie->appl_base + APPL_CTRL);
+
+	pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
+
+	return 0;
+}
+
+static const struct gpio_hotplug_slot_plat_ops tegra_pcie_gpio_hp_plat_ops = {
+	.enable = tegra_pcie_slot_enable,
+	.disable = tegra_pcie_slot_disable,
+};
+
 static const struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
 	.host_init = tegra_pcie_dw_host_init,
 };
@@ -1676,6 +1722,20 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
 	pcie->debugfs = debugfs_create_dir(name, NULL);
 	init_debugfs(pcie);
 
+	if (pcie->slot_pluggable) {
+		pcie->hp_slot.plat_ops = &tegra_pcie_gpio_hp_plat_ops;
+		pcie->hp_slot.np = pcie->dev->of_node;
+		pcie->hp_slot.slot_nr = pcie->cid;
+		pcie->hp_slot.pdev = pci_get_slot(pcie->pci.pp.bridge->bus, PCI_DEVFN(0, 0));
+
+		ret = register_gpio_hotplug_slot(&pcie->hp_slot);
+		if (ret < 0)
+			dev_warn(dev,
+				 "Failed to register platform ops for GPIO Hot-Plug controller: %d\n",
+				 ret);
+		ret = 0;
+	}
+
 	return ret;
 
 fail_host_init:
@@ -2277,6 +2337,8 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev)
 		if (!pcie->link_state && !pcie->slot_pluggable)
 			return 0;
 
+		if (pcie->slot_pluggable)
+			unregister_gpio_hotplug_slot(&pcie->hp_slot);
 		debugfs_remove_recursive(pcie->debugfs);
 		tegra_pcie_deinit_controller(pcie);
 		pm_runtime_put_sync(pcie->dev);
@@ -2398,6 +2460,8 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
 		if (!pcie->link_state && !pcie->slot_pluggable)
 			return;
 
+		if (pcie->slot_pluggable)
+			unregister_gpio_hotplug_slot(&pcie->hp_slot);
 		debugfs_remove_recursive(pcie->debugfs);
 		tegra_pcie_downstream_dev_to_D0(pcie);
 
-- 
2.17.1