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References: <20220930194923.954551-1-mmyangfl@gmail.com> <YzdRdC1qgZY+8gQk@lunn.ch>
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From:   Yangfl <mmyangfl@gmail.com>
Date:   Sat, 1 Oct 2022 04:47:42 +0800
Message-ID: <CAAXyoMNmf7YMPZYqimxJMo6W=Z-zMXHE9TjnB-SYNnpit8RV4g@mail.gmail.com>
Subject: Re: [PATCH] net: mv643xx_eth: support MII/GMII/RGMII modes
To:     Andrew Lunn <andrew@lunn.ch>
Cc:     Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>, netdev@vger.kernel.org,
        linux-kernel@vger.kernel.org
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Andrew Lunn <andrew@lunn.ch> =E4=BA=8E2022=E5=B9=B410=E6=9C=881=E6=97=A5=E5=
=91=A8=E5=85=AD 04:28=E5=86=99=E9=81=93=EF=BC=9A
>
> On Sat, Oct 01, 2022 at 03:49:23AM +0800, David Yang wrote:
> > On device reset all ports are automatically set to RGMII mode. MII
> > mode must be explicitly enabled.
> >
> > If SoC has two Ethernet controllers, by setting both of them into MII
> > mode, the first controller enters GMII mode, while the second
> > controller is effectively disabled. This requires configuring (and
> > maybe enabling) the second controller in the device tree, even though
> > it cannot be used.
> >
> > Signed-off-by: David Yang <mmyangfl@gmail.com>
> > ---
> >  drivers/net/ethernet/marvell/mv643xx_eth.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/marvell/mv643xx_eth.c b/drivers/net/e=
thernet/marvell/mv643xx_eth.c
> > index b6be0552a..e2216ce5e 100644
> > --- a/drivers/net/ethernet/marvell/mv643xx_eth.c
> > +++ b/drivers/net/ethernet/marvell/mv643xx_eth.c
> > @@ -108,6 +108,7 @@ static char mv643xx_eth_driver_version[] =3D "1.4";
> >  #define TXQ_COMMAND                  0x0048
> >  #define TXQ_FIX_PRIO_CONF            0x004c
> >  #define PORT_SERIAL_CONTROL1         0x004c
> > +#define  RGMII_EN                    0x00000008
> >  #define  CLK125_BYPASS_EN            0x00000010
> >  #define TX_BW_RATE                   0x0050
> >  #define TX_BW_MTU                    0x0058
> > @@ -1245,6 +1246,21 @@ static void mv643xx_eth_adjust_link(struct net_d=
evice *dev)
> >
> >  out_write:
> >       wrlp(mp, PORT_SERIAL_CONTROL, pscr);
> > +
> > +     /* If two Ethernet controllers present in the SoC, MII modes foll=
ow the
> > +      * following matrix:
> > +      *
> > +      * Port0 Mode   Port1 Mode      Port0 RGMII_EN  Port1 RGMII_EN
> > +      * RGMII        RGMII           1               1
> > +      * RGMII        MII/MMII        1               0
> > +      * MII/MMII     RGMII           0               1
> > +      * GMII         N/A             0               0
> > +      *
> > +      * To enable GMII on Port 0, Port 1 must also disable RGMII_EN to=
o.
> > +      */
> > +     if (!phy_interface_is_rgmii(dev->phydev))
> > +             wrlp(mp, PORT_SERIAL_CONTROL1,
> > +                  rdlp(mp, PORT_SERIAL_CONTROL1) & ~RGMII_EN);
>
> I could be reading this wrong, but doesn't this break the third line:
>
> > +      * MII/MMII     RGMII           0               1
>
> Port 1 probes first, phy_interface is rgmii, so nothing happens, port1
> RGMII_EN is left true.
>
> Port 0 then probes, MII/MMII is not RGMII, so port1 RGMII_EN is
> cleared, breaking port1.
>
> I think you need to be more specific with the comparison.
>
>   Andrew

Oh, I see. So you mean "phy-mode" property should belong to
controller, not port? I thought one controller can have at most one
port.