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References: <20220929225402.9696-1-Sergey.Semin@baikalelectronics.ru> <20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru>
Subject: Re: [PATCH RESEND v12 4/8] clk: baikal-t1: Add SATA internal ref clock buffer
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Serge Semin <fancer.lancer@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-clk@vger.kernel.org, linux-mips@vger.kernel.org,
        linux-kernel@vger.kernel.org
To:     Michael Turquette <mturquette@baylibre.com>,
        Serge Semin <Sergey.Semin@baikalelectronics.ru>
Date:   Fri, 30 Sep 2022 14:26:32 -0700
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Message-Id: <20220930212635.A4E16C433C1@smtp.kernel.org>
Precedence: bulk

Quoting Serge Semin (2022-09-29 15:53:58)
> It turns out the internal SATA reference clock signal will stay
> unavailable for the SATA interface consumer until the buffer on it's way
> is ungated. So aside with having the actual clock divider enabled we need
> to ungate a buffer placed on the signal way to the SATA controller (most
> likely some rudiment from the initial SoC release). Seeing the switch flag
> is placed in the same register as the SATA-ref clock divider at a
> non-standard ffset, let's implement it as a separate clock controller with
> the set-rate propagation to the parental clock divider wrapper. As such
> we'll be able to disable/enable and still change the original clock source
> rate.
>=20
> Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
>=20
> ---

Applied to clk-next