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References: <20221001030656.29365-1-quic_molvera@quicinc.com> <20221001030656.29365-4-quic_molvera@quicinc.com>
In-Reply-To: <20221001030656.29365-4-quic_molvera@quicinc.com>
From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date:   Sat, 1 Oct 2022 10:26:11 +0300
Message-ID: <CAA8EJpp2h3j9cPLPzCzgnYm07D5PPZg3H5_LkcXizhXt9ekkiQ@mail.gmail.com>
Subject: Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
To:     Melody Olvera <quic_molvera@quicinc.com>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
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On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
> configuration.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 3610f94bef35..39b9a00d3ad8 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
>                                 reg = <0x0 0x99c000 0x0 0x4000>;
>                                 clock-names = "se";
>                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> +                               pinctrl-names = "default";
> +                               pinctrl-0 = <&qup_uart7_default>;
>                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>                                 #address-cells = <1>;
>                                 #size-cells = <0>;
> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
>                         #hwlock-cells = <1>;
>                 };
>
> +               tlmm: pinctrl@f000000 {
> +                       compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
> +                       reg = <0x0 0xf000000 0x0 0x1000000>;
> +                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +                       gpio-ranges = <&tlmm 0 0 151>;
> +                       wakeup-parent = <&pdc>;
> +
> +                       qup_uart7_default: qup-uart7-default {
> +                               tx {
> +                                       pins = "gpio134";
> +                                       function = "qup0_se7_l2";

This looks strange. Usually we'd have a single 'qup7' function here.
I'd go back to the interconnect driver. Maybe the functions are not
correctly defined there.

> +                                       drive-strength = <2>;
> +                                       bias-disable;

'drive-strength' and 'bias-disable' are to be patched in in the board dts file.

> +                               };
> +
> +                               rx {
> +                                       pins = "gpio135";
> +                                       function = "qup0_se7_l3";
> +                                       drive-strength = <2>;
> +                                       bias-disable;
> +                               };
> +                       };
> +               };
> +
>                 pdc: interrupt-controller@b220000 {
>                         compatible = "qcom,pdc";
>                         reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> --
> 2.37.3
>


-- 
With best wishes
Dmitry