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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b15-20020a170902b60f00b00179eb71c71csi5587239pls.198.2022.10.01.09.54.14; Sat, 01 Oct 2022 09:54:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=luBhQJRC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229716AbiJAQvo (ORCPT + 99 others); Sat, 1 Oct 2022 12:51:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229775AbiJAQvT (ORCPT ); Sat, 1 Oct 2022 12:51:19 -0400 Received: from mail-yb1-xb35.google.com (mail-yb1-xb35.google.com [IPv6:2607:f8b0:4864:20::b35]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A53302F00F for ; Sat, 1 Oct 2022 09:50:48 -0700 (PDT) Received: by mail-yb1-xb35.google.com with SMTP id 81so1267057ybf.7 for ; Sat, 01 Oct 2022 09:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date; bh=g3lxI1rEb012jkHLPicQe05FcKANs5i//52fZg/FCRk=; b=luBhQJRCZ1/tzrdGyXpFnNJtdRZZfNZytLW/jVLHu4qzuikBh8atujFKR8HBcWbRAd s4rtnWo9N5G8xpkkt0kMIa29qEV5qfiy6+MYlMFzd0mo2KZENnIWsryce1i2sJr0BvUb sPlWATQIaoZmEpjvHxx2uFGqaJQjTtBoPSmpDlfByko7rK3IbydeaBf/F9S+f41D0Bxw MD/+vPbD5v+HKzuLcTNI1H0LjzbBaMiAdNlu5f4l4W24RG6FPe0J7BMLUtIGHOhYie4x 1ayGA+WoZEcyPdmHQRdqGoaKFSCGHhGRnl8dAj48kPLZyP5BiOH/JEOTXDbEU3op7vjB TbCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date; bh=g3lxI1rEb012jkHLPicQe05FcKANs5i//52fZg/FCRk=; b=NqL+1uFP1fNqhKicSFlLEnmWHwpMk1DNNOGhRUCa3M2mceZkeywXZMFXVpW41W6lCg BC7RHUdXk07Rj0jDSeorD7O3NDqz1HqGnlO6aymaOSaR1hOeu3edaWXftFer5UrnT7O+ O1KjCDXGWgcxSz8h04BIbyVvmVm2+Hf0ucGfMGqMZcxOt9g5DZCH0Kv0GUAUP9myhjxr bXpD0DaBo7M3+A/RRUK1dTK+NXEh/KJK2I9fsq5WbZy9u5lg76Pb2/hcTKbWAtNABCbB MmuS5FkL2BH6GC22Z1Xt7SVrRSZRC+hDaT5AGNOD/Ge4wbe/CTArmTjrSgbfgmu7/z/Q wuHw== X-Gm-Message-State: ACrzQf0+hj/iz+4b1DDwmONMgtyQIlclOPYNgac4k3cpfccZTDjGdcXY 5U29D3mYXtUsSr4wChoOVDYZ+nETb1RDsSS9ooyHuw== X-Received: by 2002:a25:af13:0:b0:6ae:3166:1aee with SMTP id a19-20020a25af13000000b006ae31661aeemr13068673ybh.288.1664643047860; Sat, 01 Oct 2022 09:50:47 -0700 (PDT) MIME-Version: 1.0 References: <1663157784-22232-1-git-send-email-quic_kalyant@quicinc.com> In-Reply-To: From: Dmitry Baryshkov Date: Sat, 1 Oct 2022 19:50:36 +0300 Message-ID: Subject: Re: [v5] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280 To: Kalyan Thota Cc: Doug Anderson , "Kalyan Thota (QUIC)" , "y@qualcomm.com" , dri-devel , linux-arm-msm , freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , Rob Clark , Stephen Boyd , "Vinod Polimera (QUIC)" , "Abhinav Kumar (QUIC)" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 1 Oct 2022 at 17:25, Kalyan Thota wrote: > > > >-----Original Message----- > >From: Dmitry Baryshkov > >Sent: Friday, September 30, 2022 1:59 PM > >To: Doug Anderson ; Kalyan Thota (QUIC) > > > >Cc: y@qualcomm.com; dri-devel ; linux-a= rm- > >msm ; freedreno > >; open list:OPEN FIRMWARE AND FLATTENED > >DEVICE TREE BINDINGS ; LKML >kernel@vger.kernel.org>; Rob Clark ; Stephen Boyd > >; Vinod Polimera (QUIC) > >; Abhinav Kumar (QUIC) > > > >Subject: Re: [v5] drm/msm/disp/dpu1: add support for dspp sub block flus= h in > >sc7280 > > > >WARNING: This email originated from outside of Qualcomm. Please be wary = of > >any links or attachments, and do not enable macros. > > > >On 29 September 2022 19:13:20 GMT+03:00, Doug Anderson > > wrote: > >>Hi, > >> > >>On Wed, Sep 14, 2022 at 5:16 AM Kalyan Thota > >wrote: > >>> > >>> Flush mechanism for DSPP blocks has changed in sc7280 family, it > >>> allows individual sub blocks to be flushed in coordination with > >>> master flush control. > >>> > >>> Representation: master_flush && (PCC_flush | IGC_flush .. etc ) > >>> > >>> This change adds necessary support for the above design. > >>> > >>> Changes in v1: > >>> - Few nits (Doug, Dmitry) > >>> - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) > >>> > >>> Changes in v2: > >>> - Move the address offset to flush macro (Dmitry) > >>> - Seperate ops for the sub block flush (Dmitry) > >>> > >>> Changes in v3: > >>> - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) > >>> > >>> Changes in v4: > >>> - Use shorter version for unsigned int (Stephen) > >>> > >>> Reviewed-by: Dmitry Baryshkov > >>> --- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++ > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 35 > >++++++++++++++++++++++++-- > >>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 ++++++-- > >>> 5 files changed, 50 insertions(+), 6 deletions(-) > >> > >>Breadcrumbs: though this is tagged in the subject as v5 I think the > >>newest version is actually "resend v4" [1] which just fixes the > >>Signed-off-by. > > > >Not to mention that v5 misses the S-o-B tag. > > > >> > >>[1] > >>https://lore.kernel.org/r/1663825463-6715-1-git-send-email-quic_kalyant > >>@quicinc.com > > > Latest one is https://lore.kernel.org/r/1663825463-6715-1-git-send-email-= quic_kalyant@quicinc.com that I last posted. > Don=E2=80=99t recollect on why tag was marked as v5. To avoid confusion, = shall I resend it again ? Currently I see v5 and after that comes a resend of v4. So, please send v6 with all the tags being present, no y@ in the msg-id/in-reply-to/etc. --=20 With best wishes Dmitry