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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2022 14:44:18.5334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bfd28e1-7081-4f9a-bfa2-08daa484960a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6776 X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org During system resume, translate tier2 SC7 wake sources back into irqs and do generic_handle_irq() to invoke the interrupt handlers for edge triggered wake events such as sw-wake. Signed-off-by: Prathamesh Shete Signed-off-by: Petlozu Pravareshwar --- drivers/soc/tegra/pmc.c | 42 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 66f94c011528..d166048de83c 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -3151,6 +3152,46 @@ static void wke_clear_wake_status(void) } } +/* translate sc7 wake sources back into irqs to catch edge triggered wakeups */ +static void process_wake_event(unsigned int index, unsigned long status) +{ + unsigned int irq, wake; + irq_hw_number_t hwirq; + struct irq_desc *desc; + + dev_dbg(pmc->dev, "Wake[%d:%d] status=0x%x\n", (index * 32) + 31, + index * 32, (u32)status); + + for_each_set_bit(wake, &status, 32) { + hwirq = wake + 32 * index; + + irq = irq_find_mapping(pmc->domain, hwirq); + + desc = irq_to_desc(irq); + if (!desc || !desc->action || !desc->action->name) { + dev_dbg(pmc->dev, "Resume caused by WAKE%d, irq %d\n", + (wake + 32 * index), irq); + continue; + } + dev_dbg(pmc->dev, "Resume caused by WAKE%d, %s\n", + (wake + 32 * index), desc->action->name); + generic_handle_irq(irq); + } +} + +static void tegra186_pmc_wake_syscore_resume(void) +{ + unsigned int i; + u32 status; + + for (i = 0; i < pmc->soc->max_wake_vectors; i++) { + status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)); + status = status & readl(pmc->wake + + WAKE_AOWAKE_TIER2_ROUTING(i)); + process_wake_event(i, status); + } +} + static int tegra186_pmc_wake_syscore_suspend(void) { wke_read_sw_wake_status(); @@ -3828,6 +3869,7 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = { static struct syscore_ops tegra186_pmc_wake_syscore_ops = { .suspend = tegra186_pmc_wake_syscore_suspend, + .resume = tegra186_pmc_wake_syscore_resume, }; static void tegra186_pmc_init(struct tegra_pmc *pmc) -- 2.17.1