Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20220930132033.4003377-1-foss+kernel@0leil.net>
In-Reply-To: <20220930132033.4003377-1-foss+kernel@0leil.net>
From:   Linus Walleij <linus.walleij@linaro.org>
Date:   Tue, 4 Oct 2022 09:21:48 +0200
Message-ID: <CACRpkdYOB4uy4wc+kchHioaQ+JSkoi3m6fimiLvLESRjwhaC1Q@mail.gmail.com>
Subject: Re: [PATCH v2 0/2] fix gpio-sysfs/libgpiod for rockchip
To:     Quentin Schulz <foss+kernel@0leil.net>
Cc:     brgl@bgdev.pl, heiko@sntech.de, jay.xu@rock-chips.com,
        linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
        Quentin Schulz <quentin.schulz@theobroma-systems.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Fri, Sep 30, 2022 at 3:20 PM Quentin Schulz <foss+kernel@0leil.net> wrote:

> From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
>
> Since the split of gpio and pinctrl in their own driver, gpio-sysfs and
> libgpiod userspace GPIO handling has been broken because the pins aren't
> put into their GPIO function anymore since pinctrl subsystem is
> "bypassed" when requesting GPIOs from userspace.
>
> This fixes it by making the gpio driver actually request from the
> pinctrl subsystem to put the pin in its GPIO function when the GPIO
> direction is set in userspace.
>
> I discovered the issue because we have a GPIO the user needs to control
> from userspace to flash FW on an on-board STM32 that is actually on the
> same pin as one used by the flash controller. Considering the storage
> medium tried by the BOOTROM is emmc->nor->nand->sdmmc, booting from emmc
> didn't show the issue because the default function for pins is GPIO and
> the flash controller pins didn't need to be muxed by the BOOTROM.
> However, if there's nothing on emmc, the BOOTROM does the pinmux for SPI
> controller and puts the pins in their flash mode and therefore the
> handling of that pin as a GPIO from userspace was not possible, but only
> when booting on something else than eMMC.
>
> This restores the behavior as seen in v5.14 and earlier.
>
> v2:
>  - fix missing header; reported by kernel test robot <lkp@intel.com>

Patches applied to the pinctrl tree (also the GPIO patch) as that is the
dependence point. Will go into v6.1 merge window.

Yours,
Linus Walleij