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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Tue, 4 Oct 2022 10:31:05 +0100
Message-ID: <CA+V-a8vK8KKeAvqur+CnE=SBkvYsQ7g_Gu5=v=qZ-0=VTk+RjQ@mail.gmail.com>
Subject: Re: [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache:
 Add DT binding documentation for L2 cache controller
To:     Geert Uytterhoeven <geert@linux-m68k.org>
Cc:     Conor Dooley <conor.dooley@microchip.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Magnus Damm <magnus.damm@gmail.com>,
        Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
        Philipp Tomsich <philipp.tomsich@vrull.eu>,
        Nathan Chancellor <nathan@kernel.org>,
        Atish Patra <atishp@rivosinc.com>,
        Anup Patel <apatel@ventanamicro.com>,
        linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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HI Geert,

On Tue, Oct 4, 2022 at 10:12 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Oct 4, 2022 at 9:59 AM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Oct 4, 2022 at 8:32 AM Conor Dooley <conor.dooley@microchip.com> wrote:
> > > On Tue, Oct 04, 2022 at 08:26:01AM +0100, Lad, Prabhakar wrote:
> > > > On Tue, Oct 4, 2022 at 7:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Tue, Oct 4, 2022 at 12:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
> > > > > >
> > > > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> > > > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch
> > > > > > describes the L2 cache block.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/soc/renesas/r9a07g043f-l2-cache.yaml
> > > > >
> > > > > Not andestech,ax45mp-cache.yaml?
> > > > >
> > > > I wasn't sure as we were including this in soc/renesas so named it as
> > > > r9a07g043f-l2-cache.yaml if there are no issues I'll rename it
> > > > andestech,ax45mp-cache.yaml.
> > >
> > > I may be guilty of suggesting soc/renesas in the first place, but should
> > > this maybe be in soc/andestech? I have no skin in the game, so at the
> > > end of the day it doesnt matter to me, but I would imagine that you're
> > > not going to be the only users of this l2 cache? Or is it a case of "we
> > > will deal with future users when said future users arrive"? But either
> > > way, naming it after the less specific compatible makes more sense to
> > > me.
> > >
> > As there aren't any Andestech SoCs upstream, I am in favour of keeping
> > in soc/renesas for maintenance. If in future there comes a new soc
> > from Andestech (which will go into soc/andestech) we will have to
> > split the maintenance work.
> > But anyway if there will be any users of L2 cache we could always
> > provide a config option which can be used by other SoCs.
>
> What about Documentation/devicetree/bindings/cache/?
>
Sounds good to me.

Cheers,
Prabhakar