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Date:   Tue, 4 Oct 2022 19:43:35 +0300 (EEST)
From:   =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= <ilpo.jarvinen@linux.intel.com>
To:     Lizhi Hou <lizhi.hou@amd.com>
cc:     vkoul@kernel.org, dmaengine@vger.kernel.org,
        LKML <linux-kernel@vger.kernel.org>, trix@redhat.com,
        tumic@gpxsee.org, max.zhen@amd.com, sonal.santan@amd.com,
        larry.liu@amd.com, brian.xu@amd.com
Subject: Re: [PATCH V5 XDMA 1/2] dmaengine: xilinx: xdma: Add xilinx xdma
 driver
In-Reply-To: <56f971da-5116-58dc-2df6-53ed465c8ec4@amd.com>
Message-ID: <c86fb070-9d46-9558-f7ee-216fc657cf1a@linux.intel.com>
References: <1664409507-64079-1-git-send-email-lizhi.hou@amd.com> <1664409507-64079-2-git-send-email-lizhi.hou@amd.com> <6ba2221c-bbc9-a33c-7e62-85c2d87ceeed@linux.intel.com> <56f971da-5116-58dc-2df6-53ed465c8ec4@amd.com>
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On Tue, 4 Oct 2022, Lizhi Hou wrote:

> 
> On 10/4/22 01:18, Ilpo Järvinen wrote:
> > On Wed, 28 Sep 2022, Lizhi Hou wrote:
> > 
> > > Add driver to enable PCIe board which uses XDMA (the DMA/Bridge Subsystem
> > > for PCI Express). For example, Xilinx Alveo PCIe devices.
> > >      https://www.xilinx.com/products/boards-and-kits/alveo.html
> > > 
> > > The XDMA engine support up to 4 Host to Card (H2C) and 4 Card to Host
> > > (C2H)
> > > channels. Memory transfers are specified on a per-channel basis in
> > > descriptor linked lists, which the DMA fetches from host memory and
> > > processes. Events such as descriptor completion and errors are signaled
> > > using interrupts. The hardware detail is provided by
> > >      https://docs.xilinx.com/r/en-US/pg195-pcie-dma/Introduction
> > > 
> > > This driver implements dmaengine APIs.
> > >      - probe the available DMA channels
> > >      - use dma_slave_map for channel lookup
> > >      - use virtual channel to manage dmaengine tx descriptors
> > >      - implement device_prep_slave_sg callback to handle host scatter
> > > gather
> > >        list
> > >      - implement device_config to config device address for DMA transfer
> > > 
> > > Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
> > > Signed-off-by: Sonal Santan <sonal.santan@amd.com>
> > > Signed-off-by: Max Zhen <max.zhen@amd.com>
> > > Signed-off-by: Brian Xu <brian.xu@amd.com>
> > > ---

> > > +	*chans = devm_kzalloc(&xdev->pdev->dev, sizeof(**chans) * (*chan_num),
> > > +			      GFP_KERNEL);
> > > +	if (!*chans)
> > > +		return -ENOMEM;
> > > +
> > > +	for (i = 0, j = 0; i < pdata->max_dma_channels; i++) {
> > > +		ret = xdma_read_reg(xdev, base + i * XDMA_CHAN_STRIDE,
> > > +				    XDMA_CHAN_IDENTIFIER, &identifier);
> > > +		if (ret) {
> > > +			xdma_err(xdev, "failed to read channel id: %d", ret);
> > > +			return ret;
> > > +		}
> > Is it ok to not rollback the allocation in case of an error occurs?
> 
> In this loop, the failures are returned by read/write registers. The
> read/write register failure indicates serious hardware issue and the hardware
> may not be rollback in this situation.

What I meant is that you allocated memory above (to *chans, see above). 
Shouldn't that memory be free in case the hw is not working before you 
return the error from this function?

Check also the other returns below for the same problemx.

> > > +
> > > +		if (j == *chan_num) {
> > > +			xdma_err(xdev, "invalid channel number");
> > > +			return -EIO;
> > > +		}
> > Same here?
> > 
> > > +
> > > +		/* init channel structure and hardware */
> > > +		(*chans)[j].xdev_hdl = xdev;
> > > +		(*chans)[j].base = base + i * XDMA_CHAN_STRIDE;
> > > +		(*chans)[j].dir = dir;
> > > +
> > > +		ret = xdma_channel_init(&(*chans)[j]);
> > > +		if (ret)
> > > +			return ret;
> > And here.
> > 
> > > +		(*chans)[j].vchan.desc_free = xdma_free_desc;
> > > +		vchan_init(&(*chans)[j].vchan, &xdev->dma_dev);
> > > +
> > > +		j++;
> > > +	}
> > > +
> > > +	dev_info(&xdev->pdev->dev, "configured %d %s channels", j,
> > > +		 (dir == DMA_MEM_TO_DEV) ? "H2C" : "C2H");
> > > +
> > > +	return 0;
> > > +}


-- 
 i.

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