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From:   Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To:     "clg@kaod.org" <clg@kaod.org>,
        "broonie@kernel.org" <broonie@kernel.org>,
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        Steven Lee <steven_lee@aspeedtech.com>
Subject: RE: [PATCH] spi: aspeed: Fix typo in mode_bits field for AST2600
 platform
Thread-Topic: [PATCH] spi: aspeed: Fix typo in mode_bits field for AST2600
 platform
Thread-Index: AQHY2JClpiPOsgPiCEe4cPCpJhyAZK3/dyuA
Date:   Wed, 5 Oct 2022 08:28:56 +0000
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References: <20221005080104.175769-1-chin-ting_kuo@aspeedtech.com>
In-Reply-To: <20221005080104.175769-1-chin-ting_kuo@aspeedtech.com>
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Hi All,

> -----Original Message-----
> From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> Sent: Wednesday, October 5, 2022 4:01 PM
> Subject: [PATCH] spi: aspeed: Fix typo in mode_bits field for AST2600 pla=
tform
>=20
> Both quad SPI TX and RX modes can be supported on AST2600.
> Correct typo in mode_bits field in both ast2600_fmc_data ast2600_spi_data
> structs.

A missing "and" in "both ast2600_fmc_data ast2600_spi_data structs" in the =
commit message.
It will be updated in the next version later.


Chin-Ting

>=20
> Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
> ---
>  drivers/spi/spi-aspeed-smc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c =
index
> a334e89add86..33cefcf18392 100644
> --- a/drivers/spi/spi-aspeed-smc.c
> +++ b/drivers/spi/spi-aspeed-smc.c
> @@ -1163,7 +1163,7 @@ static const struct aspeed_spi_data
> ast2500_spi_data =3D {  static const struct aspeed_spi_data ast2600_fmc_d=
ata
> =3D {
>  	.max_cs	       =3D 3,
>  	.hastype       =3D false,
> -	.mode_bits     =3D SPI_RX_QUAD | SPI_RX_QUAD,
> +	.mode_bits     =3D SPI_RX_QUAD | SPI_TX_QUAD,
>  	.we0	       =3D 16,
>  	.ctl0	       =3D CE0_CTRL_REG,
>  	.timing	       =3D CE0_TIMING_COMPENSATION_REG,
> @@ -1178,7 +1178,7 @@ static const struct aspeed_spi_data
> ast2600_fmc_data =3D {  static const struct aspeed_spi_data ast2600_spi_d=
ata
> =3D {
>  	.max_cs	       =3D 2,
>  	.hastype       =3D false,
> -	.mode_bits     =3D SPI_RX_QUAD | SPI_RX_QUAD,
> +	.mode_bits     =3D SPI_RX_QUAD | SPI_TX_QUAD,
>  	.we0	       =3D 16,
>  	.ctl0	       =3D CE0_CTRL_REG,
>  	.timing	       =3D CE0_TIMING_COMPENSATION_REG,
> --
> 2.25.1