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From:   Rahul Tanwar <rtanwar@maxlinear.com>
To:     <sboyd@kernel.org>, <mturquette@baylibre.com>,
        <linux-clk@vger.kernel.org>, <yzhu@maxlinear.com>
CC:     <linux-kernel@vger.kernel.org>, <linux-lgm-soc@maxlinear.com>,
        "Rahul Tanwar" <rtanwar@maxlinear.com>
Subject: [PATCH v3 4/4] clk: mxl: Fix a clk entry by adding relevant flags
Date:   Wed, 5 Oct 2022 17:36:38 +0800
Message-ID: <bb11192a959ac74ca440a206b9d81ea6e7717484.1664958833.git.rtanwar@maxlinear.com>
In-Reply-To: <cover.1664958833.git.rtanwar@maxlinear.com>
References: <cover.1664958833.git.rtanwar@maxlinear.com>
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Precedence: bulk

One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two
is that HW does not support enable/disable for this clk.

Handle above two limitations by adding relevant flags. Add standard
flag CLK_SET_RATE_PARENT to handle rate change and add driver internal
flag DIV_CLK_NO_MASK to handle enable/disable.

Fixes: d058fd9e8984c ("clk: intel: Add CGU clock driver for a new SoC")
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
 drivers/clk/x86/clk-cgu.c | 5 +++--
 drivers/clk/x86/clk-cgu.h | 1 +
 drivers/clk/x86/clk-lgm.c | 4 ++--
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index d24173cfe0b0..f5a99e21599e 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -164,8 +164,9 @@ static int lgm_clk_divider_enable_disable(struct clk_hw=
 *hw, int enable)
 {
 =09struct lgm_clk_divider *div =3D to_lgm_clk_divider(hw);
=20
-=09lgm_set_clk_val(div->membase, div->reg, div->shift_gate,
-=09=09=09div->width_gate, enable);
+=09if (div->flags !=3D DIV_CLK_NO_MASK)
+=09=09lgm_set_clk_val(div->membase, div->reg, div->shift_gate,
+=09=09=09=09div->width_gate, enable);
 =09return 0;
 }
=20
diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
index 73ce84345f81..bcaf8aec94e5 100644
--- a/drivers/clk/x86/clk-cgu.h
+++ b/drivers/clk/x86/clk-cgu.h
@@ -198,6 +198,7 @@ struct lgm_clk_branch {
 #define CLOCK_FLAG_VAL_INIT=09BIT(16)
 #define MUX_CLK_SW=09=09BIT(17)
 #define GATE_CLK_HW=09=09BIT(18)
+#define DIV_CLK_NO_MASK=09=09BIT(19)
=20
 #define LGM_MUX(_id, _name, _pdata, _f, _reg,=09=09\
 =09=09_shift, _width, _cf, _v)=09=09\
diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c
index e312af42e97a..4de77b2c750d 100644
--- a/drivers/clk/x86/clk-lgm.c
+++ b/drivers/clk/x86/clk-lgm.c
@@ -255,8 +255,8 @@ static const struct lgm_clk_branch lgm_branch_clks[] =
=3D {
 =09LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
 =09=09  8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
 =09LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0)=
,
-=09LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
-=09=0925, 3, 0, 0, 0, 0, dcl_div),
+=09LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR,
+=09=0925, 3, 0, 0, DIV_CLK_NO_MASK, 0, dcl_div),
 =09LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
 =09=090, 1, CLK_MUX_ROUND_CLOSEST, 0),
 =09LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",
--=20
2.17.1