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Date:   Wed, 5 Oct 2022 06:07:51 -0500
From:   Bjorn Helgaas <helgaas@kernel.org>
To:     Sathyanarayanan Kuppuswamy 
        <sathyanarayanan.kuppuswamy@linux.intel.com>
Cc:     linux-pci@vger.kernel.org, Vidya Sagar <vidyas@nvidia.com>,
        "Saheed O . Bolarinwa" <refactormyself@gmail.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Rajat Jain <rajatja@google.com>,
        "Kenneth R . Crudup" <kenny@panix.com>,
        Kai-Heng Feng <kai.heng.feng@canonical.com>,
        Abhishek Sahu <abhsahu@nvidia.com>,
        Thierry Reding <treding@nvidia.com>,
        Jonathan Hunter <jonathanh@nvidia.com>,
        Krishna Thota <kthota@nvidia.com>,
        Manikanta Maddireddy <mmaddireddy@nvidia.com>,
        Vidya Sagar <sagar.tv@gmail.com>, sagupta@nvidia.com,
        linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH 2/3] PCI/ASPM: Ignore L1 PM Substates if device lacks
 capability
Message-ID: <20221005110751.GA2275321@bhelgaas>
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On Tue, Oct 04, 2022 at 08:26:53PM -0700, Sathyanarayanan Kuppuswamy wrote:
> On 10/4/22 7:58 PM, Bjorn Helgaas wrote:
> > 187f91db8237 ("PCI/ASPM: Remove struct aspm_register_info.l1ss_cap")
> > inadvertently removed a check for existence of the L1 PM Substates (L1SS)
> > Capability before reading it.
> > 
> > If there is no L1SS Capability, this means we mistakenly read PCI_COMMAND
> > and PCI_STATUS (config address 0x04) and interpret that as the PCI_L1SS_CAP
> > register, so we may incorrectly configure L1SS.
> > 
> > Make sure the L1SS Capability exists before trying to read it.
> > 
> > Fixes: 187f91db8237 ("PCI/ASPM: Remove struct aspm_register_info.l1ss_cap")
> > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> > ---
> >  drivers/pci/pcie/aspm.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> > index 4535228e4a64..f12d117f44e0 100644
> > --- a/drivers/pci/pcie/aspm.c
> > +++ b/drivers/pci/pcie/aspm.c
> > @@ -560,6 +560,9 @@ static void aspm_l1ss_init(struct pcie_link_state *link)
> >  	u32 parent_l1ss_cap, child_l1ss_cap;
> >  	u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
> >  
> > +	if (!parent->l1ss || !child->l1ss)
> > +		return;
> 
> I have noticed that l1ss state is initialized in pci_configure_ltr(). I am
> wondering whether it is the right place? Are L1SS and LTR related?

L1SS and LTR are definitely related -- LTR supplies information
that's needed for L1.2.

I'm not sure why pci_configure_ltr() is in probe.c and
pci_bridge_reconfigure_ltr() is in pci.c; maybe it would make
sense to put them both in aspm.c.  

Bjorn