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Date:   Wed, 5 Oct 2022 13:16:03 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Andrew Cooper <Andrew.Cooper3@citrix.com>
Cc:     Rick Edgecombe <rick.p.edgecombe@intel.com>,
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Subject: Re: [PATCH v2 08/39] x86/mm: Remove _PAGE_DIRTY from kernel RO pages
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References: <20220929222936.14584-1-rick.p.edgecombe@intel.com>
 <20220929222936.14584-9-rick.p.edgecombe@intel.com>
 <8d58f57f-cece-c197-2a8b-dd02b4e405bc@citrix.com>
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On Wed, Oct 05, 2022 at 01:31:28AM +0000, Andrew Cooper wrote:
> On 29/09/2022 23:29, Rick Edgecombe wrote:
> > From: Yu-cheng Yu <yu-cheng.yu@intel.com>
> >
> > Processors sometimes directly create Write=0,Dirty=1 PTEs.
> 
> Do they? (Rhetorical)
> 
> Yes, this is a relevant anecdote for why CET isn't available on pre-TGL
> parts, but it one of the more wrong things to have as the first sentence
> of this commit message.
> 
> The point you want to express is that under the CET-SS spec, R/O+Dirty
> has a new meaning as type=shstk, so stop using this bit combination for
> existing mappings.
> 
> I'm not even sure it's relevant to note that CET capable processors can
> set D on a R/O mapping, because that depends on !CR0.WP which in turn
> prohibits CR4.CET being enabled.

Whilst I agree that the Changelog is 'suboptimal' -- I do think it might
be good to mention how we ended up at the current state where we
explicitly set this non-sensical W=0,D=1 state.

Looking at the git history this seems to be a bit of a hysterical
accident, not something done on purpose to 'optimize' for these weird
CPUs.