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[31.30.173.61]) by smtp.gmail.com with ESMTPSA id oz35-20020a1709077da300b0073022b796a7sm10495703ejc.93.2022.10.06.06.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 06:38:51 -0700 (PDT) Date: Thu, 6 Oct 2022 15:38:50 +0200 From: Andrew Jones To: Jisheng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Message-ID: <20221006133850.vkmy466uuzliobjw@kamzik> References: <20221006070818.3616-1-jszhang@kernel.org> <20221006070818.3616-9-jszhang@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221006070818.3616-9-jszhang@kernel.org> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 06, 2022 at 03:08:18PM +0800, Jisheng Zhang wrote: > All users have switched to riscv_has_extension_*, removed unused > definitions, vars and related setting code. > > Signed-off-by: Jisheng Zhang > --- > arch/riscv/include/asm/hwcap.h | 28 ---------------------------- > arch/riscv/kernel/cpufeature.c | 9 --------- Nice stats :-) > 2 files changed, 37 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 54b88ee6cae1..f52fbc121ebe 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -62,18 +62,6 @@ enum { > > extern unsigned long elf_hwcap; > > - > -/* > - * This enum represents the logical ID for each RISC-V ISA extension static > - * keys. We can use static key to optimize code path if some ISA extensions > - * are available. > - */ > -enum riscv_isa_ext_key { > - RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ > - RISCV_ISA_EXT_KEY_ZIHINTPAUSE, > - RISCV_ISA_EXT_KEY_MAX, > -}; > - > struct riscv_isa_ext_data { > /* Name of the extension displayed to userspace via /proc/cpuinfo */ > char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; > @@ -81,22 +69,6 @@ struct riscv_isa_ext_data { > unsigned int isa_ext_id; > }; > > -extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX]; > - > -static __always_inline int riscv_isa_ext2key(int num) > -{ > - switch (num) { > - case RISCV_ISA_EXT_f: > - return RISCV_ISA_EXT_KEY_FPU; > - case RISCV_ISA_EXT_d: > - return RISCV_ISA_EXT_KEY_FPU; > - case RISCV_ISA_EXT_ZIHINTPAUSE: > - return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; > - default: > - return -EINVAL; > - } > -} Yay! One less extension mapping to track! > - > static __always_inline bool > riscv_has_extension_likely(const unsigned long ext) > { > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 2b1f18f97253..6bc3fb749274 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -28,9 +28,6 @@ unsigned long elf_hwcap __read_mostly; > /* Host ISA bitmap */ > static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > -DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); > -EXPORT_SYMBOL(riscv_isa_ext_keys); > - > /** > * riscv_isa_extension_base() - Get base extension word > * > @@ -242,12 +239,6 @@ void __init riscv_fill_hwcap(void) > if (elf_hwcap & BIT_MASK(i)) > print_str[j++] = (char)('a' + i); > pr_info("riscv: ELF capabilities %s\n", print_str); > - > - for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) { > - j = riscv_isa_ext2key(i); > - if (j >= 0) > - static_branch_enable(&riscv_isa_ext_keys[j]); > - } > } > > #ifdef CONFIG_RISCV_ALTERNATIVE > -- > 2.37.2 > Reviewed-by: Andrew Jones