Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Thu, 06 Oct 2022 19:58:05 -0700 (PDT)
Subject:     Re: [PATCH 1/3] dt-bindings: sifive-ccache: rename SiFive L2 cache to composible cache
In-Reply-To: <20220829062202.3287-2-zong.li@sifive.com>
CC:     robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        aou@eecs.berkeley.edu, greentime.hu@sifive.com,
        conor.dooley@microchip.com, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
        zong.li@sifive.com
From:   Palmer Dabbelt <palmer@dabbelt.com>
To:     zong.li@sifive.com
Message-ID: <mhng-050016e5-0f50-4366-b4bd-98b4b36a56bb@palmer-ri-x1c9>
Mime-Version: 1.0 (MHng)
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 8bit
Precedence: bulk

On Sun, 28 Aug 2022 23:22:00 PDT (-0700), zong.li@sifive.com wrote:
> Since composible cache may be L3 cache if private L2 cache exists, it
> should use its original name composible cache to prevent confusion.
>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  .../riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml}      | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive-ccache.yaml} (92%)
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> similarity index 92%
> rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> rename to Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> index 69cdab18d629..1a64a5384e36 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive-ccache.yaml
> @@ -12,8 +12,8 @@ maintainers:
>    - Paul Walmsley  <paul.walmsley@sifive.com>
>
>  description:
> -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> +  The SiFive Composable Cache Controller is used to provide access to fast copies
> +  of memory for masters in a Core Complex. The Composable Cache Controller also
>    acts as directory-based coherency manager.
>    All the properties in ePAPR/DeviceTree specification applies for this platform.
>
> @@ -27,6 +27,7 @@ select:
>          enum:
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> +          - sifive,ccache0

Looks like Rob's bot had comments and I don't see a v2.  Sorry if I'm 
missing something.

Also: I'd guess that we only had the SOC-specific mappings on purpose.  
It's kind of a grey area and I'm OK either way, but I'd definately 
prefer the DT folks to get a chance to review these.  My guess is that 
they're not looking due to the bot comments, but sorry again if I've 
missed it.

>    required:
>      - compatible
> @@ -37,6 +38,7 @@ properties:
>        - enum:
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> +          - sifive,ccache0
>        - const: cache
>
>    cache-block-size: