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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id t3-20020a17090340c300b00172e19c5f8bsm341162pld.168.2022.10.06.20.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 20:05:30 -0700 (PDT) Date: Thu, 06 Oct 2022 20:05:30 -0700 (PDT) X-Google-Original-Date: Thu, 06 Oct 2022 20:05:28 PDT (-0700) Subject: Re: [PATCH] riscv: enable THP_SWAP for RV64 In-Reply-To: CC: jszhang@kernel.org, Paul Walmsley , aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org From: Palmer Dabbelt To: conor.dooley@microchip.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 05 Oct 2022 23:53:03 PDT (-0700), conor.dooley@microchip.com wrote: > On Wed, Oct 05, 2022 at 07:35:53PM -0700, Palmer Dabbelt wrote: >> On Sun, 21 Aug 2022 10:05:59 PDT (-0700), jszhang@kernel.org wrote: >> > I have a Sipeed Lichee RV dock board which only has 512MB DDR, so >> > memory optimizations such as swap on zram are helpful. As is seen >> > in commit d0637c505f8a ("arm64: enable THP_SWAP for arm64") and >> > commit bd4c82c22c367e ("mm, THP, swap: delay splitting THP after >> > swapped out"), THP_SWAP can improve the swap throughput significantly. >> > >> > Enable THP_SWAP for RV64, testing the micro-benchmark which is >> > introduced by commit d0637c505f8a ("arm64: enable THP_SWAP for arm64") >> > shows below numbers on the Lichee RV dock board: >> > >> > thp swp throughput w/o patch: 66908 bytes/ms (mean of 10 tests) >> > thp swp throughput w/ patch: 322638 bytes/ms (mean of 10 tests) >> > >> > Improved by 382%! >> > >> > Signed-off-by: Jisheng Zhang >> > --- >> > arch/riscv/Kconfig | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> > index ed66c31e4655..19088c750c7f 100644 >> > --- a/arch/riscv/Kconfig >> > +++ b/arch/riscv/Kconfig >> > @@ -45,6 +45,7 @@ config RISCV >> > select ARCH_WANT_FRAME_POINTERS >> > select ARCH_WANT_GENERAL_HUGETLB >> > select ARCH_WANT_HUGE_PMD_SHARE if 64BIT >> > + select ARCH_WANTS_THP_SWAP if TRANSPARENT_HUGEPAGE >> > select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU >> > select BUILDTIME_TABLE_SORT if MMU >> > select CLONE_BACKWARDS >> >> Thanks, this is on for-next. > > FYI, this is v1 of a patchset that went to v3. > v3 only changed the commit message, but v2 had a functional change. > > v3 is here: > https://lore.kernel.org/all/20220829145742.3139-1-jszhang@kernel.org/ Thanks, not sure why I missed those. I've put the v3 on for-next.