Received: by 2002:a05:6359:c8b:b0:c7:702f:21d4 with SMTP id go11csp408538rwb; Thu, 6 Oct 2022 21:18:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6GAvUZTmsC4B71EY+2X2vwFbq7kTyM2M8iJoUbAzUGkGRPvL4QF/L1zZTSsmpK2eIR/euX X-Received: by 2002:aa7:c04d:0:b0:454:2f81:b966 with SMTP id k13-20020aa7c04d000000b004542f81b966mr2780050edo.269.1665116330929; Thu, 06 Oct 2022 21:18:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665116330; cv=none; d=google.com; s=arc-20160816; b=rLrM2bYvnVnKUf7ymfzTHQt+AEpg7PWAzx4idiQckS1bCr1WYTNIjhQYk94u3jagDj Ze+ofabJQILOGrTN5OqZnbeS9mODWfZ2zE8m/2gDiBSvwVVtaRXAFjRyO43jq5fEiHNi SHqlpUdQdESZjWhbUkzb72fGUXbTpsNZgAdHv1oYVzPTHXfl44gaX5wCycAzeo6DY1tl lnbJnZ6rzbv098pl0C73FHO5NwRaLSC+rSrsuWnDUQhWaBWudrBO/nBzZFOWzW300IVX 92L6P6Qi0Vn76yxIO+yEjvEKZEbliF9txQ8Fv3yF6f6k7RSLuO32KnB1l7k7plkPFmHr TloA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qMKJuaTLhE4s3eyZKvtuxa4KC0GqOHEf6ga/NZ+IM/I=; b=ImL9BQ6rJ3yPbpxxEXIOgxZK0f5ZvXnllyAVLjTm92W1gVuAm3o0i7OU3WqCNNTLTe vDJz/kFz+qEyjAggCnQ/wC2gQoz4jQNZMrL9BT28Ph20ys0FY5XN7fZIqiuFw3xrj+j7 PZ7ukZE6MF0AN6LgCcLUp+LEfGIVIKA2SkuBmIq9ah3op+v/IWnFS91OMTWQoxaAoCjC yuM34gqOsmFiDq6iSiCNQG9rwIjCT/Y0GLfd/brk15Mln6qAiAGqurRZo97SThEE065R vfZGhTgZ14V7NRwXh7EDrU+53YA/5/RojXRd3ezJBA7MlKtdNmmByxD+aXadzRodx7su HnQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=mYfwBMBZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k2-20020a056402048200b00448ce617058si765734edv.463.2022.10.06.21.18.22; Thu, 06 Oct 2022 21:18:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=mYfwBMBZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229674AbiJGDSC (ORCPT + 99 others); Thu, 6 Oct 2022 23:18:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229665AbiJGDRu (ORCPT ); Thu, 6 Oct 2022 23:17:50 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33AC8CAE4A; Thu, 6 Oct 2022 20:17:43 -0700 (PDT) X-UUID: 48e8fd33375f40b0bd2854b1d250fe1b-20221007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qMKJuaTLhE4s3eyZKvtuxa4KC0GqOHEf6ga/NZ+IM/I=; b=mYfwBMBZO4ERuyG60iJDMi2gTZ2Jb+K/oe2Tp80D5vmGxm7Ds7lsGiM5x7Zrre63mqz+D30YvU9h6qc0lUX5tvA00aWBI2sn/idLWMoYf5rHQnsFys6n3K170HyDQkzgKcWhLPScBPMERIo5pEkrMhdwDjIo89HqH5Apq14mRB8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:c28162ba-3c04-4473-b2e0-9620e05ab1ec,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:c28162ba-3c04-4473-b2e0-9620e05ab1ec,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:16f92be1-2948-402a-a6e4-b5d31fe11eb7,B ulkID:221007111740BO6M6PFX,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 48e8fd33375f40b0bd2854b1d250fe1b-20221007 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1840736981; Fri, 07 Oct 2022 11:17:39 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 7 Oct 2022 11:17:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 7 Oct 2022 11:17:38 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , , , , , Moudy Ho Subject: [PATCH v1 1/6] media: platform: mtk-mdp3: add chip configuration header file Date: Fri, 7 Oct 2022 11:17:32 +0800 Message-ID: <20221007031737.5125-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221007031737.5125-1-moudy.ho@mediatek.com> References: <20221007031737.5125-1-moudy.ho@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY, URIBL_CSS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to be compatible with more MDP3 chip settings in the future, move the chip-related configuration to a separate header file. Signed-off-by: Moudy Ho --- .../media/platform/mediatek/mdp3/mt8183_mdp.h | 35 +++++++++++++++++++ .../platform/mediatek/mdp3/mtk-mdp3-core.c | 27 ++------------ 2 files changed, 37 insertions(+), 25 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mt8183_mdp.h diff --git a/drivers/media/platform/mediatek/mdp3/mt8183_mdp.h b/drivers/media/platform/mediatek/mdp3/mt8183_mdp.h new file mode 100644 index 000000000000..a75400c8a12b --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mt8183_mdp.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MT8183_MDP_H__ +#define __MT8183_MDP_H__ + +static const struct mdp_platform_config mt8183_plat_cfg = { + .rdma_support_10bit = true, + .rdma_rsz1_sram_sharing = true, + .rdma_upsample_repeat_only = true, + .rsz_disable_dcm_small_sample = false, + .wrot_filter_constraint = false, +}; + +static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = { + [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" }, + [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8183-disp-mutex" }, + [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" } +}; + +static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { + [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, + [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, + [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1, + [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0, + [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0, + [MDP_COMP_WDMA] = MUTEX_MOD_IDX_MDP_WDMA, + [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0, + [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0, +}; + +#endif // __MT8183_MDP_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 2d1f6ae9f080..e720e1564991 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -12,33 +12,10 @@ #include #include #include + #include "mtk-mdp3-core.h" #include "mtk-mdp3-m2m.h" - -static const struct mdp_platform_config mt8183_plat_cfg = { - .rdma_support_10bit = true, - .rdma_rsz1_sram_sharing = true, - .rdma_upsample_repeat_only = true, - .rsz_disable_dcm_small_sample = false, - .wrot_filter_constraint = false, -}; - -static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = { - [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" }, - [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8183-disp-mutex" }, - [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" } -}; - -static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { - [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0, - [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0, - [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1, - [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0, - [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0, - [MDP_COMP_WDMA] = MUTEX_MOD_IDX_MDP_WDMA, - [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0, - [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0, -}; +#include "mt8183_mdp.h" static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_probe_infra = mt8183_mdp_probe_infra, -- 2.18.0