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Date:   Fri, 7 Oct 2022 17:09:34 +0200
From:   Peter Zijlstra <peterz@infradead.org>
To:     Xin Li <xin3.li@intel.com>
Cc:     linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
        mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
        hpa@zytor.com
Subject: Re: [PATCH 6/6] x86/gsseg: use the LKGS instruction if available for
 load_gs_index()
Message-ID: <Y0BBLhHrgxYZahfi@hirez.programming.kicks-ass.net>
References: <20221006154041.13001-1-xin3.li@intel.com>
 <20221006154041.13001-7-xin3.li@intel.com>
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On Thu, Oct 06, 2022 at 08:40:41AM -0700, Xin Li wrote:
>  static inline void native_load_gs_index(unsigned int selector)
>  {
> +	u16 sel = selector;
> +
> +	/*
> +	 * Note: the fixup is used for the LKGS instruction, but
> +	 * it needs to be attached to the primary instruction sequence
> +	 * as it isn't something that gets patched.
> +	 *
> +	 * %rax is provided to the assembly routine as a scratch
> +	 * register.
> +	 */
> +	alternative_io("1: call asm_load_gs_index\n"
> +		       ".pushsection \".fixup\",\"ax\"\n"
> +		       "2:	xorl %k[sel], %k[sel]\n"
> +		       "	jmp 1b\n"
> +		       ".popsection\n"
> +		       _ASM_EXTABLE(1b, 2b),
> +		       _ASM_BYTES(0x3e) LKGS_DI,
> +		       X86_FEATURE_LKGS,
> +		       ASM_OUTPUT2([sel] "+D" (sel), ASM_CALL_CONSTRAINT),
> +		       ASM_NO_INPUT_CLOBBER(_ASM_AX));
>  }

Something like so perhaps?

	asm_inline volatile("1:\n"
			    ALTERNATIVE("call asm_load_gs_index\n",
					LKGS_DI,
					X86_FEATURE_LKGS)
			    _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])
			    : ASM_CALL_CONSTRAINT
			    : [sel] "D" (sel)
			    : "memory", _ASM_AX);


(completely untested, not even seen a compiler upclose)