Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Colin Foster <colin.foster@in-advantage.com>
To:     netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org
Cc:     Russell King <linux@armlinux.org.uk>, UNGLinuxDriver@microchip.com,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Claudiu Manoil <claudiu.manoil@nxp.com>,
        Paolo Abeni <pabeni@redhat.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Eric Dumazet <edumazet@google.com>,
        "David S. Miller" <davem@davemloft.net>,
        Vladimir Oltean <olteanv@gmail.com>,
        Florian Fainelli <f.fainelli@gmail.com>,
        Vivien Didelot <vivien.didelot@gmail.com>,
        Andrew Lunn <andrew@lunn.ch>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>, Lee Jones <lee@kernel.org>
Subject: [RFC v4 net-next 17/17] mfd: ocelot: add external ocelot switch control
Date:   Sat,  8 Oct 2022 11:51:52 -0700
Message-Id: <20221008185152.2411007-18-colin.foster@in-advantage.com>
In-Reply-To: <20221008185152.2411007-1-colin.foster@in-advantage.com>
References: <20221008185152.2411007-1-colin.foster@in-advantage.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?sjr42qKEc+jBc7gZd9D23XgRt5agneV7yJtW5jaD8Pv+8+neY0MXTabykVYF?=
 =?us-ascii?Q?lb3DV0N3MYGshiaub+rItoozs2M6hZerre25eVEQIFOykIqKJgqUPYl/geOk?=
 =?us-ascii?Q?DdwEey+ueRIy+jVGQRrD/cABr7b4QcJofFDQpNiNFUxRs6gwmI2jW5zvXiGM?=
 =?us-ascii?Q?lZ37yz1EWFzfFsr+n/fd1V1FReaQDLX0Kfrjvv/Zs3rQwhTbya1eOZckVXIk?=
 =?us-ascii?Q?TjC0AgNhVHLI7lSaGWqVWDDjkpSK1ThzgdQe+doU/vGPcGLY8yKAAxUhInJT?=
 =?us-ascii?Q?nMv7CBHfMrUBOM7ssOLrM9LS2WFR04prU1mZVRi03MfDpwE+5zKhoBx22lCI?=
 =?us-ascii?Q?KVwP3vwu4JEjNkW0m3TU06k7KI/mQWeinlNjdorPKpJX8opcZsnBn2WZWjTb?=
 =?us-ascii?Q?0lp+krURwWSAx5mMNrBi5uVboLkiR+uBrFPYzzeay+0v/E4D66r0Oa8bTxMM?=
 =?us-ascii?Q?KG3JcJFohrRgOEJFjgZ5eVtqLA5aGXeKwo0VKW/lXEVV8gVf3Wmn1kGJQgML?=
 =?us-ascii?Q?NmCCV1JQoBYzJoe1gCY1nLQjXo4VQJSyotxIGYsMeItGM/PgtV5CV/kC7m8p?=
 =?us-ascii?Q?3fvcLMPprZ0lPxnyBZkSborypuY+tr6XKZN73f8qSiDjoBSQ/a0bEeIf711w?=
 =?us-ascii?Q?Xi1I0u5kLY4G43fkKs8uTaoaTM54ZfyoGjfZvMbVJ4GkkyAoM8mGJpy6m/F6?=
 =?us-ascii?Q?DkVSfWCjShMydrnyiPfqjO0pG/95o+OFXnTWvQeppAxAvdP9m/HJNy5a485T?=
 =?us-ascii?Q?1rAdlLl3jPCKVH6WG9PsGUjGY1DwXS4KncNkScqAgUO6f3K8/PNy1y7oyWFS?=
 =?us-ascii?Q?o8RYSsnA9pFVwajOc2S332ITMSWM9CI69NlE+5VP8mLKTkds/dDVPm5iaSvY?=
 =?us-ascii?Q?DeqXZtWom/yRemxyhDbUZw8MhZ6sAAjm3Y3Sd7Jd2yt9o6Q5kyFFZoWSu+GX?=
 =?us-ascii?Q?HtptnvMeNAm7o/fG3bFih9wb6Oz4MV/vWAiXP6lD3gQpZfM+TT+jz0WGFuED?=
 =?us-ascii?Q?s8Qy5sbDgZ8yBfYNGWuNogKEz+bJ3ks/TsYfV9N3ZnI1WbxVt7STdAKG18y/?=
 =?us-ascii?Q?EnE9ei/jeBOAxvOv2R2jL/bbYjC3uMELkqJpMlr1yGQwnFF+HUh4CmNU37r/?=
 =?us-ascii?Q?ymAadeLIT8P2xxrnQXSGW3yFCQ8fzPKPtBXRVoqJJV5SpeFhyw7/4c2wdeU7?=
 =?us-ascii?Q?GdJwG0Xa1kZ/k0hwUwzdr5psAyTBrzOxJjtGn2mGSy7obwJ4CkQfJuYfX9gX?=
 =?us-ascii?Q?ypY93fkfFhwWMnpC/k1ABMciW+BlbsUgnhguUl4gIEFkbf0AMjah5ceO4OwQ?=
 =?us-ascii?Q?KFpHqg+tBDbtbG4q3XW4n5gLEvsxgBvv1QjcdPcWQhL7M0o7Ufo25KScSDok?=
 =?us-ascii?Q?WtlZuuZktTCk8kYJ19ut2gMuMwwIkJFPWRnvsTILJ1k6s9zaTN/9odLldj6X?=
 =?us-ascii?Q?FD9kRcWKCwKCYRGqRLh1vsYscJgK3yqw/A/roLSrNmOqy1AAJ1J7qBdZDF/Q?=
 =?us-ascii?Q?3GTO3gHD/WduGRV+4r0Tug0uPcB025zvZhE7e+Bdg2hogNQU/H5Nz3/aUTxG?=
 =?us-ascii?Q?s/w57gW4/d1syUeR1mwvy1CIqCi1hqBdxfkmY1zwNNLnPHVQ71jGCcIO/o24?=
 =?us-ascii?Q?YqQ/Qbw6+WhuV83++9ZEtNc=3D?=
X-OriginatorOrg: in-advantage.com
X-MS-Exchange-CrossTenant-Network-Message-Id: cb37ee54-4735-41c9-04ce-08daa95e3617
X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2022 18:52:12.7250
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: POAsih8R0JdjLru4JnSQ2NUyADEqmRNMkFqzmGB4LOyGXinWfdbBCSPmcW90dNbjYfkUXMP4NEW1ONMC0l8y6Gk+fT8PcF5gJAKKPHqkPzU=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR10MB6506
X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Utilize the existing ocelot MFD interface to add switch functionality to
the Microsemi VSC7512 chip.

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---

v4
    * Integrate a different patch, so now this one
      - Adds the resources during this patch. Previouisly this
        was done in a separate patch
      - Utilize the standard {,num_}resources initializer

v3
    * No change

v2
    * New patch, broken out from a previous one

---
 drivers/mfd/ocelot-core.c | 60 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c
index 013e83173062..f35b4b2d4eec 100644
--- a/drivers/mfd/ocelot-core.c
+++ b/drivers/mfd/ocelot-core.c
@@ -45,6 +45,39 @@
 #define VSC7512_SIO_CTRL_RES_START	0x710700f8
 #define VSC7512_SIO_CTRL_RES_SIZE	0x00000100
 
+#define VSC7512_ANA_RES_START		0x71880000
+#define VSC7512_ANA_RES_SIZE		0x00010000
+
+#define VSC7512_QS_RES_START		0x71080000
+#define VSC7512_QS_RES_SIZE		0x00000100
+
+#define VSC7512_QSYS_RES_START		0x71800000
+#define VSC7512_QSYS_RES_SIZE		0x00200000
+
+#define VSC7512_REW_RES_START		0x71030000
+#define VSC7512_REW_RES_SIZE		0x00010000
+
+#define VSC7512_SYS_RES_START		0x71010000
+#define VSC7512_SYS_RES_SIZE		0x00010000
+
+#define VSC7512_S0_RES_START		0x71040000
+#define VSC7512_S1_RES_START		0x71050000
+#define VSC7512_S2_RES_START		0x71060000
+#define VCAP_RES_SIZE			0x00000400
+
+#define VSC7512_PORT_0_RES_START	0x711e0000
+#define VSC7512_PORT_1_RES_START	0x711f0000
+#define VSC7512_PORT_2_RES_START	0x71200000
+#define VSC7512_PORT_3_RES_START	0x71210000
+#define VSC7512_PORT_4_RES_START	0x71220000
+#define VSC7512_PORT_5_RES_START	0x71230000
+#define VSC7512_PORT_6_RES_START	0x71240000
+#define VSC7512_PORT_7_RES_START	0x71250000
+#define VSC7512_PORT_8_RES_START	0x71260000
+#define VSC7512_PORT_9_RES_START	0x71270000
+#define VSC7512_PORT_10_RES_START	0x71280000
+#define VSC7512_PORT_RES_SIZE		0x00010000
+
 #define VSC7512_GCB_RST_SLEEP_US	100
 #define VSC7512_GCB_RST_TIMEOUT_US	100000
 
@@ -96,6 +129,28 @@ static const struct resource vsc7512_sgpio_resources[] = {
 	DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"),
 };
 
+static const struct resource vsc7512_switch_resources[] = {
+	DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, OCELOT_RES_NAME_ANA),
+	DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, OCELOT_RES_NAME_QS),
+	DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, OCELOT_RES_NAME_QSYS),
+	DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, OCELOT_RES_NAME_REW),
+	DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, OCELOT_RES_NAME_SYS),
+	DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VCAP_RES_SIZE, OCELOT_RES_NAME_S0),
+	DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VCAP_RES_SIZE, OCELOT_RES_NAME_S1),
+	DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VCAP_RES_SIZE, OCELOT_RES_NAME_S2),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"),
+	DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10")
+};
+
 static const struct mfd_cell vsc7512_devs[] = {
 	{
 		.name = "ocelot-pinctrl",
@@ -121,6 +176,11 @@ static const struct mfd_cell vsc7512_devs[] = {
 		.use_of_reg = true,
 		.num_resources = ARRAY_SIZE(vsc7512_miim1_resources),
 		.resources = vsc7512_miim1_resources,
+	}, {
+		.name = "ocelot-switch",
+		.of_compatible = "mscc,vsc7512-switch",
+		.num_resources = ARRAY_SIZE(vsc7512_switch_resources),
+		.resources = vsc7512_switch_resources,
 	},
 };
 
-- 
2.25.1