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Date:   Mon, 10 Oct 2022 19:53:52 +0530
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Subject: Re: [PATCH v3 2/5] PCI: tegra194: Move dw_pcie_ep_linkup() to
 threaded IRQ handler
Content-Language: en-US
To:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        kishon@kernel.org, lpieralisi@kernel.org, bhelgaas@google.com
Cc:     linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        kw@linux.com, robh@kernel.org, vigneshr@ti.com
References: <20221006134927.41437-1-manivannan.sadhasivam@linaro.org>
 <20221006134927.41437-3-manivannan.sadhasivam@linaro.org>
From:   Vidya Sagar <vidyas@nvidia.com>
In-Reply-To: <20221006134927.41437-3-manivannan.sadhasivam@linaro.org>
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 =?utf-8?B?blNIMzdyOFZVR0d3SGV6ZXZSdkRsVTVtS3BUMXU1dmpyb3hWWFd3YTlYZFFP?=
 =?utf-8?B?b3JSM2x6ejhnV2hjSXlpeGtQd1BwcDgybTg0V1NYWGd6dWZoMStrU0NvL1hE?=
 =?utf-8?B?WmhzaExoa1h2dThpQjNvWGZkWFhkWVJLbmQ3Tjc3MGNkUXF5bktKZnlMSHd1?=
 =?utf-8?B?a3l1bVc3MnFkZ053eC81OHQrcmlGNTh5c3FMMndXMytLSEpINE5IU0ppcjRE?=
 =?utf-8?B?OW1nWlpabVZmaVduQXlQSm1GNTB6YW9ScmY2VFVoRmVSbmlOa0U5bmdqU0lu?=
 =?utf-8?B?N2x1bjFwV2xOZXlvdUt5UGN4cEJkZXI5aFpoeWk2TTVPK1MwTnRHTDd2dkFS?=
 =?utf-8?B?eUthYUZWQ1lxVnl1WFNkb3AwR0Q2ZXNaNEFnQlBWdzBtRU5FeW1Bd3VXMzFt?=
 =?utf-8?B?a2hqNW1wK1FpY3hEcm4xQ1N6UkQ2bVBXalJVT243UHlZd2xHQXdXOGhtZ2hV?=
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 =?utf-8?B?TE1CLzlqUklXVHpva0lKNjJHaWlYbWd2Wmo1d3ZOTWFyMkZGKzNpVTcvcEJL?=
 =?utf-8?B?M3dyaHFLeWlza3hKTGdycTQ3cjQ0VlJaN0R0OGdYUjUrRU1md2FjeGYrRTZi?=
 =?utf-8?B?R0x5Y3NBRjBJdngySE1ZRjZKdk9MWTRYVzIzWmNQb1BTOEQ3ZVg2UmxXVEd0?=
 =?utf-8?B?SExKcFVtcVZvMHY4RnFXdmNaSVRCVWVtWXV2UktFMGJzMDhrV3c4UFdYNmxx?=
 =?utf-8?B?V0ZzVy9JcXFPT1l5SFpzTW9yclBOMHZ0aXp5MWswTFJ2bVQ4RFBhU0VaSVFz?=
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 =?utf-8?B?OUs4UWh6R0JlYkUwRUQxbDZVUEQ5VkJyejZ0V2RLWlhUTjhOK2lNVkVSTEdN?=
 =?utf-8?B?QlJSWEt2ci9NTVZGMXJPRlNQYitTY2pEVkRDZm5VMTlxUE9OL2hJdUFJNmtz?=
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Hi Mani,
Thanks for your change. One comment though.

On 10/6/2022 7:19 PM, Manivannan Sadhasivam wrote:
> External email: Use caution opening links or attachments
> 
> 
> dw_pcie_ep_linkup() may take more time to execute depending on the EPF
> driver implementation. Calling this API in the hard IRQ handler is not
> encouraged since the hard IRQ handlers are supposed to complete quickly.
> 
> So move the dw_pcie_ep_linkup() call to threaded IRQ handler.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>   drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 1b6b437823d2..6a487f52e1fb 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -287,6 +287,7 @@ struct tegra_pcie_dw {
>          struct gpio_desc *pex_refclk_sel_gpiod;
>          unsigned int pex_rst_irq;
>          int ep_state;
> +       long link_status;
>   };
> 
>   static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
> @@ -450,9 +451,13 @@ static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
>   static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
>   {
>          struct tegra_pcie_dw *pcie = arg;
> +       struct dw_pcie_ep *ep = &pcie->pci.ep;
>          struct dw_pcie *pci = &pcie->pci;
>          u32 val, speed;
> 
> +       if (test_and_clear_bit(0, &pcie->link_status))
> +               dw_pcie_ep_linkup(ep);
> +
>          speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
>                  PCI_EXP_LNKSTA_CLS;
>          clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
> @@ -499,7 +504,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
>   static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   {
>          struct tegra_pcie_dw *pcie = arg;
> -       struct dw_pcie_ep *ep = &pcie->pci.ep;
>          int spurious = 1;
>          u32 status_l0, status_l1, link_status;
> 
> @@ -515,7 +519,7 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>                          link_status = appl_readl(pcie, APPL_LINK_STATUS);
>                          if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) {
>                                  dev_dbg(pcie->dev, "Link is up with Host\n");
> -                               dw_pcie_ep_linkup(ep);
> +                               set_bit(0, &pcie->link_status);

irq thread needs to be woken up at this point. So, please add
return IRQ_WAKE_THREAD;

Thanks,
Vidya Sagar

>                          }
>                  }
> 
> --
> 2.25.1
>