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From:   Rahul Tanwar <rtanwar@maxlinear.com>
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Subject: Re: [PATCH RESEND] x86/devicetree: Add support for boot time
 interrupt mode config
Thread-Topic: [PATCH RESEND] x86/devicetree: Add support for boot time
 interrupt mode config
Thread-Index: AQHY1wejNb5MBDY3IkOIWGU+3msB+A==
Date:   Tue, 11 Oct 2022 03:59:55 +0000
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References: <20221003090750.10348-1-rtanwar@maxlinear.com>
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On 3/10/2022 5:08 pm, Rahul Tanwar wrote:=0A> Presently, init/boot time int=
errupt delivery mode is enumerated only=0A> for ACPI enabled systems by par=
sing MADT table or for older systems=0A> by parsing MP table. But for OF ba=
sed x86 systems, it is assumed &=0A> fixed to legacy PIC mode.=0A>=20=0A> A=
dd support for configuration of init time interrupt delivery mode=0A> for x=
86 OF based systems by introducing a new boolean property=0A> 'intel,no-imc=
r' for interrupt-controller node of local APIC. This=0A> property emulates =
IMCRP Bit 7 of MP feature info byte 2 of MP=0A> floating pointer structure.=
=0A>=20=0A> Defaults to legacy PIC mode if absent. Configures it to virtual=
 wire=0A> compatibility mode if present.=0A>=20=0A=0A=0AAny comments or con=
cerns for this patch? IMHO, this configurability of=20=0Apic_mode was missi=
ng for OF systems & it should benefit other x86 based=20=0AOF platforms as =
well. Please let me know if i am missing anything about=20=0Ait or if you h=
ave other concerns.=0A=0AThanks,=0ARahul=0A=0A=0A> Signed-off-by: Rahul Tan=
war <rtanwar@maxlinear.com>=0A> ---=0A>   arch/x86/kernel/devicetree.c | 10=
 +++++++++-=0A>   1 file changed, 9 insertions(+), 1 deletion(-)=0A>=20=0A>=
 diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c=
=0A> index 5cd51f25f446..de14015317f8 100644=0A> --- a/arch/x86/kernel/devi=
cetree.c=0A> +++ b/arch/x86/kernel/devicetree.c=0A> @@ -167,7 +167,15 @@ st=
atic void __init dtb_lapic_setup(void)=0A>   =09=09=09return;=0A>   =09}=0A=
>   =09smp_found_config =3D 1;=0A> -=09pic_mode =3D 1;=0A> +=09if (of_prope=
rty_read_bool(dn, "intel,no-imcr")) {=0A> +=09=09pr_info("    Virtual Wire =
compatibility mode.\n");=0A> +=09=09pic_mode =3D 0;=0A> +=09}=0A> +=09else =
{=0A> +=09=09pr_info("    IMCR and PIC compatibility mode.\n");=0A> +=09=09=
pic_mode =3D 1;=0A> +=09}=0A> +=0A>   =09register_lapic_address(lapic_addr)=
;=0A>   }=0A>  =20=0A=0A