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Date:   Mon, 10 Oct 2022 21:20:58 -0700
From:   "H. Peter Anvin" <hpa@zytor.com>
To:     Brian Gerst <brgerst@gmail.com>, Xin Li <xin3.li@intel.com>
CC:     linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
        mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com,
        peterz@infradead.org
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2_6/6=5D_x86/gsseg=3A_use_the_LKGS_?= =?US-ASCII?Q?instruction_if_available_for_load=5Fgs=5Findex=28=29?=
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On October 10, 2022 8:51:33 PM PDT, Brian Gerst <brgerst@gmail=2Ecom> wrote=
:
>On Mon, Oct 10, 2022 at 3:46 PM Xin Li <xin3=2Eli@intel=2Ecom> wrote:
>>
>> From: "H=2E Peter Anvin (Intel)" <hpa@zytor=2Ecom>
>>
>> The LKGS instruction atomically loads a segment descriptor into the
>> %gs descriptor registers, *except* that %gs=2Ebase is unchanged, and th=
e
>> base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
>> what we want this function to do=2E
>>
>> Signed-off-by: H=2E Peter Anvin (Intel) <hpa@zytor=2Ecom>
>> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead=2Eorg>
>> Signed-off-by: Xin Li <xin3=2Eli@intel=2Ecom>
>> link: https://lkml=2Eorg/lkml/2022/10/7/352
>> link: https://lkml=2Eorg/lkml/2022/10/7/373
>> ---
>>  arch/x86/include/asm/gsseg=2Eh | 27 ++++++++++++++++++++++++++-
>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/include/asm/gsseg=2Eh b/arch/x86/include/asm/gsse=
g=2Eh
>> index 5e3b56a17098=2E=2E4aaef7a1d68f 100644
>> --- a/arch/x86/include/asm/gsseg=2Eh
>> +++ b/arch/x86/include/asm/gsseg=2Eh
>> @@ -3,15 +3,40 @@
>>  #define _ASM_X86_GSSEG_H
>>
>>  #include <linux/types=2Eh>
>> +
>> +#include <asm/asm=2Eh>
>> +#include <asm/cpufeature=2Eh>
>> +#include <asm/alternative=2Eh>
>>  #include <asm/processor=2Eh>
>> +#include <asm/nops=2Eh>
>>
>>  #ifdef CONFIG_X86_64
>>
>>  extern asmlinkage void asm_load_gs_index(u16 selector);
>>
>> +/* Replace with "lkgs %di" once binutils support LKGS instruction */
>> +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)
>> +
>>  static inline void native_load_gs_index(unsigned int selector)
>>  {
>> -       asm_load_gs_index(selector);
>> +       u16 sel =3D selector;
>> +
>> +       /*
>> +        * Note: the fixup is used for the LKGS instruction, but
>> +        * it needs to be attached to the primary instruction sequence
>> +        * as it isn't something that gets patched=2E
>> +        *
>> +        * %rax is provided to the assembly routine as a scratch
>> +        * register=2E
>> +        */
>> +       asm_inline volatile("1:\n"
>> +                           ALTERNATIVE("call asm_load_gs_index\n",
>> +                                       _ASM_BYTES(0x3e) LKGS_DI,
>> +                                       X86_FEATURE_LKGS)
>> +                           _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_=
REG, %k[sel])
>> +                           : ASM_CALL_CONSTRAINT
>> +                           : [sel] "D" (sel)
>
>DI needs to be marked as input and output (+D), since the exception
>handler modifies it=2E
>
>> +                           : "memory", _ASM_AX);
>
>_ASM_AX is only needed for code that is used by both 32 and 64-bit=2E
>Since this is 64-bit only, "rax" would be appropriate=2E
>
>--
>Brian Gerst

The practice seems to have been to prefer the macros for consistency=2E