Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Tue, 11 Oct 2022 18:55:08 +0200
From:   Pali =?utf-8?B?Um9ow6Fy?= <pali@kernel.org>
To:     Jon Hunter <jonathanh@nvidia.com>
Cc:     Thierry Reding <thierry.reding@gmail.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Rob Herring <robh@kernel.org>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Vidya Sagar <vidyas@nvidia.com>, linux-tegra@vger.kernel.org,
        linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro
Message-ID: <20221011165508.ezpwvmzmxywqoj4u@pali>
References: <20220928121911.14994-1-pali@kernel.org>
 <220b0fe7-8b7b-cf9b-e28d-d9d81647fb80@nvidia.com>
 <20221011161638.ycxpg3ox2wv63vym@pali>
 <18a48407-9fd7-175d-0c7f-5702b077f13d@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
Content-Transfer-Encoding: 8bit
In-Reply-To: <18a48407-9fd7-175d-0c7f-5702b077f13d@nvidia.com>
User-Agent: NeoMutt/20180716
Precedence: bulk

On Tuesday 11 October 2022 17:47:50 Jon Hunter wrote:
> On 11/10/2022 17:16, Pali Rohár wrote:
> 
> ...
> 
> > I see, this is stupid mistake. PCIe config read and write operations
> > needs to be 4-byte aligned, so normally it is done by calculating 4-byte
> > aligned base address and then using appropriate cpu load/store
> > instruction to access just defined size/offset of 4-byte config space
> > register.
> > 
> > pci-tegra.c is using common helper functions pci_generic_config_read()
> > and pci_generic_config_write(), which expects final address with offset,
> > and not 4-byte aligned address.
> > 
> > I'm not sure what should be the proper fix, but for me it looks like
> > that pci_generic_config_read() and pci_generic_config_write() could be
> > adjusted to handle it.
> > 
> > In any case, above patch is a regressions and I see there two options
> > for now:
> > 
> > 1) Reverting that patch
> > 
> > 2) Adding "offset |= where & 0x3;" after the PCI_CONF1_EXT_ADDRESS()
> >     macro to set also lower 2 bits of accessed register.
> > 
> > Jon, Lorenzo, what do you think? Could you test if 2) is working fine?
> 
> 
> I tested 'offset |= where & 0xff' which is essentially the same as the above
> and that is working and so I am sure that the above works too. However, I do
> wonder if reverting is simpler because we already have a '&
> ~PCI_CONF1_ENABLE' and now adding '| where & 0x3' seems to diminish the
> value of this change.
> 
> Cheers
> Jon
> 
> -- 
> nvpublic

Well, if decision would be that pci_generic_config_read() could be
modified in the future to handle aligning, then '|= where & 0x3' block
would be moved from driver to generic function...

I'm really not sure which option to choose.