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Date:   Tue, 11 Oct 2022 16:17:52 -0700
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Subject: Re: [PATCH 2/2] efi/cper, cxl: Decode CXL Error Log
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To:     Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc:     linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
        Alison Schofield <alison.schofield@intel.com>,
        Vishal Verma <vishal.l.verma@intel.com>,
        Ira Weiny <ira.weiny@intel.com>,
        Ben Widawsky <bwidawsk@kernel.org>,
        Dan Williams <dan.j.williams@intel.com>,
        Robert Richter <rrichter@amd.com>,
        Yazen Ghannam <yazen.ghannam@amd.com>,
        Terry Bowman <terry.bowman@amd.com>
References: <20221007211714.71129-1-Smita.KoralahalliChannabasappa@amd.com>
 <20221007211714.71129-3-Smita.KoralahalliChannabasappa@amd.com>
 <20221010153415.00004bc0@huawei.com>
From:   Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
In-Reply-To: <20221010153415.00004bc0@huawei.com>
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On 10/10/2022 7:34 AM, Jonathan Cameron wrote:
> On Fri, 7 Oct 2022 21:17:14 +0000
> Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> wrote:
>
>
>> +
>> +	if (prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG) {
>> +		size_t size = sizeof(*prot_err) + prot_err->dvsec_len;
>> +		struct ras_capability_regs *cxl_ras;
>> +
>> +		pr_info("%s Error log length: 0x%04x\n", pfx, prot_err->err_len);
>> +
>> +		pr_info("%s CXL Error Log:\n", pfx);
>> +		cxl_ras = (struct ras_capability_regs *)((long)prot_err + size);
>> +		pr_info("%s cxl_ras_uncor_status: 0x%08x, cxl_ras_uncor_mask: 0x%08x\n",
>> +			pfx, cxl_ras->uncor_status, cxl_ras->uncor_mask);
> Is it worth splitting these up, so that we get a human readable line with the
> individual fields broken out?

Will do.

>
>> +		pr_info("%s cxl_ras_uncor_severity: 0x%08x\n", pfx,
>> +			cxl_ras->uncor_severity);
>> +		pr_info("%s cxl_ras_cor_status: 0x%08x, cxl_ras_cor_mask: 0x%08x\n",
>> +			pfx, cxl_ras->cor_status, cxl_ras->cor_mask);
> Not outputting the cap_control register?  Some of that might be useful.

Will add.

>
>> +		pr_info("%s Header Log Registers:\n", pfx);
>> +		print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, cxl_ras->header_log,
>> +			       sizeof(cxl_ras->header_log), 0);
>> +	}
>>   }
>> diff --git a/include/linux/cxl_err.h b/include/linux/cxl_err.h
>> new file mode 100644
>> index 000000000000..c89dbb6c286f
>> --- /dev/null
>> +++ b/include/linux/cxl_err.h
>> @@ -0,0 +1,21 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (C) 2022 Advanced Micro Devices, Inc.
>> + *
>> + * Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
>> + */
>> +
>> +#ifndef LINUX_CXL_ERR_H
>> +#define LINUX_CXL_ERR_H
>> +
>> +struct ras_capability_regs {
> CXL r3.0 Spec reference plus prefix it with cxl_

Okay.

>
> Agreed with your comment at the top. Some discussion needed on where to
> put this - or whether to delay figuring that out until a later stage.

Yes, more discussion needed here though!

Thanks,
Smita

>
>> +	u32 uncor_status;
>> +	u32 uncor_mask;
>> +	u32 uncor_severity;
>> +	u32 cor_status;
>> +	u32 cor_mask;
>> +	u32 cap_control;
>> +	u32 header_log[16];
>> +};
>> +
>> +#endif //__CXL_ERR_