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Message-ID: <b209b4a7-5de4-8ad6-4e99-8fff63397abd@huawei.com>
Date:   Wed, 12 Oct 2022 10:50:11 +0800
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Subject: Re: [PATCH v2] clk: at91: fix the build with binutils 2.27
Content-Language: en-US
To:     Nicolas Ferre <nicolas.ferre@microchip.com>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        Claudiu Beznea <claudiu.beznea@microchip.com>,
        <linux-clk@vger.kernel.org>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, Stephen Boyd <sboyd@kernel.org>
References: <20221012030635.13140-1-wangkefeng.wang@huawei.com>
From:   Kefeng Wang <wangkefeng.wang@huawei.com>
In-Reply-To: <20221012030635.13140-1-wangkefeng.wang@huawei.com>
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On 2022/10/12 11:06, Kefeng Wang wrote:
> There is an issue when build with older versions of binutils 2.27.0,
>
> arch/arm/mach-at91/pm_suspend.S: Assembler messages:
> arch/arm/mach-at91/pm_suspend.S:1086: Error: garbage following instruction -- `ldr tmp1,=0x00020010UL'
>
> Use UL() macro to fix the issue in assembly file.
>
> Fixes: 4fd36e458392 ("ARM: at91: pm: add plla disable/enable support for sam9x60")
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> v2: use linux/bits.h instead of vdso/bits.h
+ Stephen
>
>   include/linux/clk/at91_pmc.h | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
> index 3484309b59bf..7af499bdbecb 100644
> --- a/include/linux/clk/at91_pmc.h
> +++ b/include/linux/clk/at91_pmc.h
> @@ -12,6 +12,8 @@
>   #ifndef AT91_PMC_H
>   #define AT91_PMC_H
>   
> +#include <linux/bits.h>
> +
>   #define AT91_PMC_V1		(1)			/* PMC version 1 */
>   #define AT91_PMC_V2		(2)			/* PMC version 2 [SAM9X60] */
>   
> @@ -45,8 +47,8 @@
>   #define	AT91_PMC_PCSR		0x18			/* Peripheral Clock Status Register */
>   
>   #define AT91_PMC_PLL_ACR	0x18			/* PLL Analog Control Register [for SAM9X60] */
> -#define		AT91_PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL	/* Default PLL ACR value for UPLL */
> -#define		AT91_PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL	/* Default PLL ACR value for PLLA */
> +#define		AT91_PMC_PLL_ACR_DEFAULT_UPLL	UL(0x12020010)	/* Default PLL ACR value for UPLL */
> +#define		AT91_PMC_PLL_ACR_DEFAULT_PLLA	UL(0x00020010)	/* Default PLL ACR value for PLLA */
>   #define		AT91_PMC_PLL_ACR_UTMIVR		(1 << 12)	/* UPLL Voltage regulator Control */
>   #define		AT91_PMC_PLL_ACR_UTMIBG		(1 << 13)	/* UPLL Bandgap Control */
>