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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y24-20020a056402171800b004596d6e78e3si13800550edu.144.2022.10.12.02.12.42; Wed, 12 Oct 2022 02:13:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Y1VTEKdH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229583AbiJLJIo (ORCPT + 99 others); Wed, 12 Oct 2022 05:08:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229612AbiJLJIa (ORCPT ); Wed, 12 Oct 2022 05:08:30 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5406632C for ; Wed, 12 Oct 2022 02:08:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1665565709; x=1697101709; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=frqKpQ/GfZmnAadzzaN+14iYXqvO5TCT0DXBBbMT2eA=; b=Y1VTEKdH6X3hpl1BWG4EyK2S/NLBEa9G0Fgghy00Oms74edvWdGy0PrL 1KnGyxhTKes44LGmPpmOhcK53JHV+ceG3ZfqGiVuVjVm/eqi2DhnUsJ4p wLm/f2QPjnHDs57k03nXLhePuIb45bCfSOZnytUUnoA6hGqsW1f5m0z07 1TXUf0WSysbM5lEs0TqbUylCP5cVmveIJLzishdtxp1GhCdASOJ/cQW/F dn+uRuTGWPeKi+8pGI+ysuKuKjd9gcA2D22z2vahugYruG7p9yMSwnYUf x6gvcpHySUsi7sYSBsvIM0k028/+vPWdSMBl6sXDxYNscN6TYwfuju7jQ Q==; X-IronPort-AV: E=Sophos;i="5.95,178,1661842800"; d="scan'208";a="184456017" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 12 Oct 2022 02:08:27 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 12 Oct 2022 02:08:27 -0700 Received: from wendy (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12 via Frontend Transport; Wed, 12 Oct 2022 02:08:26 -0700 Date: Wed, 12 Oct 2022 10:08:03 +0100 From: Conor Dooley To: Andrew Jones CC: , , Palmer Dabbelt , Paul Walmsley , Albert Ou , Yury Norov Subject: Re: [PATCH v2] RISC-V: Fix /proc/cpuinfo cpumask warning Message-ID: References: <20221012082949.1801222-1-ajones@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20221012082949.1801222-1-ajones@ventanamicro.com> X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 12, 2022 at 10:29:49AM +0200, Andrew Jones wrote: > Commit 78e5a3399421 ("cpumask: fix checking valid cpu range") has > started issuing warnings[*] when cpu indices equal to nr_cpu_ids - 1 > are passed to cpumask_next* functions. seq_read_iter() and cpuinfo's > start and next seq operations implement a pattern like > > n = cpumask_next(n - 1, mask); > show(n); > while (1) { > ++n; > n = cpumask_next(n - 1, mask); > if (n >= nr_cpu_ids) > break; > show(n); > } > > which will issue the warning when reading /proc/cpuinfo. Ensure no > warning is generated by validating the cpu index before calling > cpumask_next(). > > [*] Warnings will only appear with DEBUG_PER_CPU_MAPS enabled. > > Signed-off-by: Andrew Jones > Cc: Yury Norov Reviewed-by: Conor Dooley Tested-by: Conor Dooley Thanks > --- > v2: > - Got comments on the x86 equivalent patch and made the same > changes to this one > - Added all the information I should have in the first place > to the commit message [Boris] > - Changed style of fix [Boris] > > > arch/riscv/kernel/cpu.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 4aa8cd749441..63138b880b92 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -166,6 +166,9 @@ static void print_mmu(struct seq_file *f) > > static void *c_start(struct seq_file *m, loff_t *pos) > { > + if (*pos >= nr_cpu_ids) > + return NULL; > + > *pos = cpumask_next(*pos - 1, cpu_online_mask); > if ((*pos) < nr_cpu_ids) > return (void *)(uintptr_t)(1 + *pos); > -- > 2.37.3 >