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Date:   Wed, 12 Oct 2022 23:21:02 +0800
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Subject: Re: [PATCH v1 12/30] dt-bindings: reset: Add starfive,jh7110-reset
 bindings
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To:     Conor Dooley <conor.dooley@microchip.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Rob Herring <robh@kernel.org>, linux-riscv@lists.infradead.org,
        devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
        linux-gpio@vger.kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Stephen Boyd <sboyd@kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        linux-kernel@vger.kernel.org
References: <20220929143225.17907-1-hal.feng@linux.starfivetech.com>
 <20220929175147.19749-1-hal.feng@linux.starfivetech.com>
 <20220929184349.GA2551443-robh@kernel.org>
 <8BEAFAD2C4CE6E4A+0a00376c-1e3e-f597-bcf6-106ff294859a@linux.starfivetech.com>
 <2f1d1afd-3c97-6ce0-8247-6e1c4a24e548@linaro.org>
 <4769BE3503398017+b1699221-ccc9-a0c1-0b11-141ce9644d74@linux.starfivetech.com>
 <9f04267d-2592-b303-9b79-9cef672c970a@linaro.org> <Y0bJkGQklX+eOGyW@wendy>
From:   Hal Feng <hal.feng@linux.starfivetech.com>
In-Reply-To: <Y0bJkGQklX+eOGyW@wendy>
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On Wed, 12 Oct 2022 15:05:04 +0100, Conor Dooley wrote:
> Hey Hal Feng,
> 
> On Wed, Oct 12, 2022 at 09:33:42AM -0400, Krzysztof Kozlowski wrote:
> > >>> These two properties are the key differences among different reset controllers.
> > >>
> > >> Different as in different compatibles? Please answer the questions..> 
> > >>> There are five memory regions for clock and reset in StarFive JH7110 SoC. They
> > >>> are "syscrg", "aoncrg", "stgcrg", "ispcrg" and "voutcrg". Each memory region
> > >>> has different reset ASSERT/STATUS register offset and different number of reset
> > >>> signals. 
> > >>
> > >> Then these are not exactly the same devices, so using one compatible for
> > >> them does not look correct.
> > > 
> > > One compatible can just be matched by one device? I think this is what
> > > confuses me.
> > 
> > I don't understand the question.
> 
> If two SoCs have exactly the same device/peripheral then they _can_ use
> the same compatible. If they share some common, viable feature-set then
> one can "fall back" to the other depending on what your Venn diagram of
> common features looks like. I've not been following this too closely,
> but I think what Krzysztof is suggesting is that you have a jh7100 and
> a jh7110 compatible. Then in your driver you just "know" that if you
> match against jh7110 which values to use for register offsets & vice
> versa for a match against the jh7100. There's many examples over the
> tree for how to handle this sort of thing rather than including it in
> the devicetree.
> 
> Maybe Rob and Krzysztof will scream at me for this description, but
> devicetree is about how periperhals etc are connected together in the
> system not about the internals of a given peripheral.
> 
> Following that logic, the devicetree should not contain register offsets
> etc that are a known quanitity once you've determined that you are running
> on vendor,soc-foo.
> 
> Hopefully that helps with your confusion somewhat?
> Conor.

Yes, anyway, thank you for the detailed reply.

Best regards,
Hal