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Date:   Thu, 13 Oct 2022 06:29:03 +0100
From:   Conor Dooley <conor@kernel.org>
To:     linux-riscv@lists.infradead.org, Sasha Levin <sashal@kernel.org>,
        linux-kernel@vger.kernel.org, stable@vger.kernel.org
CC:     Conor Dooley <conor.dooley@microchip.com>,
        Daire McNamara <daire.mcnamara@microchip.com>,
        Claudiu Beznea <claudiu.beznea@microchip.com>,
        mturquette@baylibre.com, sboyd@kernel.org,
        linux-clk@vger.kernel.org
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_AUTOSEL_6=2E0_20/67=5D_clk=3A_microc?= =?US-ASCII?Q?hip=3A_mpfs=3A_add_MSS_pll=27s_set_=26_round_rate?=
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Not a fix, NAK=2E Same for 5=2E19=2E

On 13 October 2022 01:15:01 IST, Sasha Levin <sashal@kernel=2Eorg> wrote:
>From: Conor Dooley <conor=2Edooley@microchip=2Ecom>
>
>[ Upstream commit 14016e4aafc5f157c10fb1a386fa3b3bd9c30e9a ]
>
>The MSS pll is not a fixed frequency clock, so add set() & round_rate()
>support=2E
>Control is limited to a 7 bit output divider as other devices on the
>FPGA occupy the other three outputs of the PLL & prevent changing
>the multiplier=2E
>
>Reviewed-by: Daire McNamara <daire=2Emcnamara@microchip=2Ecom>
>Signed-off-by: Conor Dooley <conor=2Edooley@microchip=2Ecom>
>Reviewed-by: Claudiu Beznea <claudiu=2Ebeznea@microchip=2Ecom>
>Signed-off-by: Claudiu Beznea <claudiu=2Ebeznea@microchip=2Ecom>
>Link: https://lore=2Ekernel=2Eorg/r/20220909123123=2E2699583-9-conor=2Edo=
oley@microchip=2Ecom
>Signed-off-by: Sasha Levin <sashal@kernel=2Eorg>
>---
> drivers/clk/microchip/clk-mpfs=2Ec | 54 ++++++++++++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
>diff --git a/drivers/clk/microchip/clk-mpfs=2Ec b/drivers/clk/microchip/c=
lk-mpfs=2Ec
>index b6b89413e090=2E=2Ecb4ec4749279 100644
>--- a/drivers/clk/microchip/clk-mpfs=2Ec
>+++ b/drivers/clk/microchip/clk-mpfs=2Ec
>@@ -126,8 +126,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(str=
uct clk_hw *hw, unsigned lon
> 	return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
> }
>=20
>+static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long =
rate, unsigned long *prate)
>+{
>+	struct mpfs_msspll_hw_clock *msspll_hw =3D to_mpfs_msspll_clk(hw);
>+	void __iomem *mult_addr =3D msspll_hw->base + msspll_hw->reg_offset;
>+	void __iomem *ref_div_addr =3D msspll_hw->base + REG_MSSPLL_REF_CR;
>+	u32 mult, ref_div;
>+	unsigned long rate_before_ctrl;
>+
>+	mult =3D readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
>+	mult &=3D clk_div_mask(MSSPLL_FBDIV_WIDTH);
>+	ref_div =3D readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
>+	ref_div &=3D clk_div_mask(MSSPLL_REFDIV_WIDTH);
>+
>+	rate_before_ctrl =3D rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
>+
>+	return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POS=
TDIV_WIDTH,
>+				  msspll_hw->flags);
>+}
>+
>+static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rat=
e, unsigned long prate)
>+{
>+	struct mpfs_msspll_hw_clock *msspll_hw =3D to_mpfs_msspll_clk(hw);
>+	void __iomem *mult_addr =3D msspll_hw->base + msspll_hw->reg_offset;
>+	void __iomem *ref_div_addr =3D msspll_hw->base + REG_MSSPLL_REF_CR;
>+	void __iomem *postdiv_addr =3D msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
>+	u32 mult, ref_div, postdiv;
>+	int divider_setting;
>+	unsigned long rate_before_ctrl, flags;
>+
>+	mult =3D readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
>+	mult &=3D clk_div_mask(MSSPLL_FBDIV_WIDTH);
>+	ref_div =3D readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
>+	ref_div &=3D clk_div_mask(MSSPLL_REFDIV_WIDTH);
>+
>+	rate_before_ctrl =3D rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
>+	divider_setting =3D divider_get_val(rate_before_ctrl, prate, NULL, MSSP=
LL_POSTDIV_WIDTH,
>+					  msspll_hw->flags);
>+
>+	if (divider_setting < 0)
>+		return divider_setting;
>+
>+	spin_lock_irqsave(&mpfs_clk_lock, flags);
>+
>+	postdiv =3D readl_relaxed(postdiv_addr);
>+	postdiv &=3D ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHI=
FT);
>+	writel_relaxed(postdiv, postdiv_addr);
>+
>+	spin_unlock_irqrestore(&mpfs_clk_lock, flags);
>+
>+	return 0;
>+}
>+
> static const struct clk_ops mpfs_clk_msspll_ops =3D {
> 	=2Erecalc_rate =3D mpfs_clk_msspll_recalc_rate,
>+	=2Eround_rate =3D mpfs_clk_msspll_round_rate,
>+	=2Eset_rate =3D mpfs_clk_msspll_set_rate,
> };
>=20
> #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) {	=
		\