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References: <20221009181338.2896660-8-lis8215@gmail.com> <202210100607.YdxoR0tD-lkp@intel.com>
In-Reply-To: <202210100607.YdxoR0tD-lkp@intel.com>
From:   Siarhei Volkau <lis8215@gmail.com>
Date:   Thu, 13 Oct 2022 09:37:37 +0300
Message-ID: <CAKNVLfaFvge4A8-QUzeq-JManpuYMGvyHXCJi-ew==CWN8-M=A@mail.gmail.com>
Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the
 JZ4750/JZ4755 SoCs
To:     kernel test robot <lkp@intel.com>
Cc:     kbuild-all@lists.01.org,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Vinod Koul <vkoul@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Paul Cercueil <paul@crapouillou.net>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        Jiri Slaby <jirislaby@kernel.org>, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        dmaengine@vger.kernel.org, linux-serial@vger.kernel.org,
        linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org
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=D0=BF=D0=BD, 10 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 01:29, kernel test=
 robot <lkp@intel.com>:
> config: ia64-allyesconfig
> config: arm64-randconfig-r035-20221010

>  > 142  #define CGU_REG_CPCCR   ((void *)CKSEG1ADDR(0x10000000))

> 0-DAY CI Kernel Test Service

I know CKSEG1ADDR is MIPS specific, might be it needed to disable COMPILE_T=
EST
on the driver?
Since early syscon isn't mainlined yet I don't see any other way at the mom=
ent.

Any suggestions on that, folks?