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From:   Rahul Tanwar <rtanwar@maxlinear.com>
To:     <sboyd@kernel.org>, <mturquette@baylibre.com>,
        <linux-clk@vger.kernel.org>, <yzhu@maxlinear.com>
CC:     <linux-kernel@vger.kernel.org>, <linux-lgm-soc@maxlinear.com>,
        "Rahul Tanwar" <rtanwar@maxlinear.com>
Subject: [PATCH v4 3/4] clk: mxl: Add option to override gate clks
Date:   Thu, 13 Oct 2022 14:48:32 +0800
Message-ID: <bdc9c89317b5d338a6c4f1d49386b696e947a672.1665642720.git.rtanwar@maxlinear.com>
In-Reply-To: <cover.1665642720.git.rtanwar@maxlinear.com>
References: <cover.1665642720.git.rtanwar@maxlinear.com>
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Precedence: bulk

In MxL's LGM SoC, gate clocks can be controlled either from CGU clk driver
i.e. this driver or directly from power management driver/daemon. It is
dependent on the power policy/profile requirements of the end product.

To support such use cases, provide option to override gate clks enable/disa=
ble
by adding a flag GATE_CLK_HW which controls if these gate clks are controll=
ed
by HW i.e. this driver or overridden in order to allow it to be controlled
by power profiles instead.

Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
---
 drivers/clk/x86/clk-cgu.c | 15 ++++++++++++++-
 drivers/clk/x86/clk-cgu.h |  1 +
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 1f7e93de67bc..5eafd7e0d945 100644
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -354,8 +354,21 @@ int lgm_clk_register_branches(struct lgm_clk_provider =
*ctx,
 =09=09=09hw =3D lgm_clk_register_fixed_factor(ctx, list);
 =09=09=09break;
 =09=09case CLK_TYPE_GATE:
-=09=09=09hw =3D lgm_clk_register_gate(ctx, list);
+=09=09=09if (list->gate_flags & GATE_CLK_HW)
+=09=09=09=09hw =3D lgm_clk_register_gate(ctx, list);
+=09=09=09else
+=09=09=09=09/*
+=09=09=09=09 * GATE_CLKs can be controlled either from
+=09=09=09=09 * CGU clk driver i.e. this driver or directly
+=09=09=09=09 * from power management driver/daemon. It is
+=09=09=09=09 * dependent on the power policy/profile requirements
+=09=09=09=09 * of the end product. To override control of gate
+=09=09=09=09 * clks from this driver, provide NULL for this index
+=09=09=09=09 * of gate clk provider.
+=09=09=09=09 */
+=09=09=09=09hw =3D NULL;
 =09=09=09break;
+
 =09=09default:
 =09=09=09dev_err(ctx->dev, "invalid clk type\n");
 =09=09=09return -EINVAL;
diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
index 0aa0f35d63a0..73ce84345f81 100644
--- a/drivers/clk/x86/clk-cgu.h
+++ b/drivers/clk/x86/clk-cgu.h
@@ -197,6 +197,7 @@ struct lgm_clk_branch {
 /* clock flags definition */
 #define CLOCK_FLAG_VAL_INIT=09BIT(16)
 #define MUX_CLK_SW=09=09BIT(17)
+#define GATE_CLK_HW=09=09BIT(18)
=20
 #define LGM_MUX(_id, _name, _pdata, _f, _reg,=09=09\
 =09=09_shift, _width, _cf, _v)=09=09\
--=20
2.17.1