Received: by 2002:a05:6358:1087:b0:cb:c9d3:cd90 with SMTP id j7csp601623rwi; Thu, 13 Oct 2022 02:38:06 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7CGc911bzcylCaP/ZdbKJj5puXl4hM/lmmJAhLw/HgRoOHZPin8OHcRYPhbqDf09BjSOd1 X-Received: by 2002:a17:90a:8c8e:b0:202:883b:2644 with SMTP id b14-20020a17090a8c8e00b00202883b2644mr10043173pjo.89.1665653885870; Thu, 13 Oct 2022 02:38:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665653885; cv=none; d=google.com; s=arc-20160816; b=nXwwgUs6fq40YYpTP/00Y8WmM6G6IO7d+usmYk8oYxiJkriNqO9u4RAImpWeJco/nQ RSX9hw/D2qmywGAhtwE2AilGV0/wusOg4Uf2GaYaGgXdJHXmtO9xvaKeV8oMLMcvk2jS NXG8IG4O4xISp95qDe0+sq7YeJojNjQqNLePUL/uFjNi+sWdcNTbFI165gq+jS/wBfmc dEZNWHdTyfdEsM5n48kBsWZg97gy45A9xKzSfdm/psmSCS4aKctbjFGCYnCFYYutIC+j ct+2WNpNwe02rfr4RCjWZtH4tHjWnqURQw6uc8qwC3ASjMGMGrJtpbiQXMhJgcXuS3bf 1SzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :feedback-id:dkim-signature:dkim-signature; bh=qmzT73Nu8Eo80tOnAkFbYbAqOXBysXSE5lE905g1TjE=; b=WnEt8qv0++P27V1U+t0XE1HjxTD9Wz+zIsoMHNcI6gxsmjHWfWfUNJFF/q6/TSGWp+ wQU8mzn2tyqXLZy6pr9kPNXRDWGdf7yW50qcUVyREerI98X+mQYMt+ZlIBBWM2cCmTHi 5aALlkhtqH2btQFhU3ygtJsFGLiuHKV7N55lPNtP8jEXntUg1CR68RqDw42qKtP1hlaY F0lKCeXqXB7ZfpjvqOTL3Rx8/1HOu4y2taYwJUWlqV6OWw6HaX0m1AJMY+pcbXG9yRB3 75E0Qfu+905Gh07TQRIMc/DYm3LP0/cP9VXV/SbaYylBDTio7tzrMgPh4+n0kRYYMhUy Ia9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm3 header.b=dl3+WEg5; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=AnQIVh1b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r30-20020a63a55e000000b0043c5dfca83esi22696527pgu.19.2022.10.13.02.37.53; Thu, 13 Oct 2022 02:38:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@cerno.tech header.s=fm3 header.b=dl3+WEg5; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=AnQIVh1b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=cerno.tech Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229971AbiJMJOG (ORCPT + 99 others); Thu, 13 Oct 2022 05:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229883AbiJMJNe (ORCPT ); Thu, 13 Oct 2022 05:13:34 -0400 Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCE65141117; Thu, 13 Oct 2022 02:13:23 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.nyi.internal (Postfix) with ESMTP id DE78B5C0162; Thu, 13 Oct 2022 05:13:22 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Thu, 13 Oct 2022 05:13:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h=cc :cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1665652402; x= 1665738802; bh=qmzT73Nu8Eo80tOnAkFbYbAqOXBysXSE5lE905g1TjE=; b=d l3+WEg5YQS895fzP8Iv6T22TGg5de4JRmgwkSHgT7i8T688LZn8IkrjHppYsoP8k AvHpHaXwiviVbWxbKthEKPGfUq7fXfNRSv3P2gyxCP0VeRkC7019rv2SCCLhSOIB HyTNvS3V5bWCVpF6PenHg8ZIvrUoJLTqVvLpCKLElkqDR9Lxtc+oe2JpKNPA+oIe eJXWF+Gyq/Q5jF7bJ02a7aevmbB8UEkKyv7fs5wtfuL8TqUEZFSMUyY3XBJpRXg7 kgkSdVdkHCnyYiuTvH30EfveL/INnexP3VFugT2uqolu/snmRKNgcpTEvbVykqOM Iq+VB5mPTjULSzsYrQMhQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1665652402; x= 1665738802; bh=qmzT73Nu8Eo80tOnAkFbYbAqOXBysXSE5lE905g1TjE=; b=A nQIVh1bP0qcIsXkAlIvQ1h2kQA4MYkCxHMQzomBmSaq+X17CxBXpaOZBdiTB5Fg3 oRYOe4bvHU4EYG9en5v9+mEbq3rLldPkJ6E8RUKG+boHTlKPuDXKCEbO4mxqbuto Q1HlBQD6gOOCJlZBJCTin8nYKk/gEET0v0ub9k8MBiMTYjIGoEbg41w3HdwSjIu4 834no9bp4dZwTPzVOLsdbd7D4wlDtcyA3V/krL1bVUvpLxyQH+RnQBPWYWq2Ofwv HzJp4//sAPxXNANwxjJsxRb7QoteIT8EgutlxrDMeSveKejNAOMc5pIRhVo5skWd KEHFMSjxsJlLKBFRqHupQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrfeektddgudegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephfffufggtgfgkfhfjgfvvefosehtkeertdertdejnecuhfhrohhmpeforgig ihhmvgcutfhiphgrrhguuceomhgrgihimhgvsegtvghrnhhordhtvggthheqnecuggftrf grthhtvghrnhepudduudfhveejteefgedvffdvvedvjedugedukeejhedtlefhffevtefh jeeltdevnecuvehluhhsthgvrhfuihiivgepudenucfrrghrrghmpehmrghilhhfrhhomh epmhgrgihimhgvsegtvghrnhhordhtvggthh X-ME-Proxy: Feedback-ID: i8771445c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 13 Oct 2022 05:13:22 -0400 (EDT) From: Maxime Ripard Date: Thu, 13 Oct 2022 11:13:13 +0200 Subject: [PATCH v3 6/7] drm/vc4: hdmi: Add more checks for 4k resolutions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220815-rpi-fix-4k-60-v3-6-fc56729d11fe@cerno.tech> References: <20220815-rpi-fix-4k-60-v3-0-fc56729d11fe@cerno.tech> In-Reply-To: <20220815-rpi-fix-4k-60-v3-0-fc56729d11fe@cerno.tech> To: Florian Fainelli , Michael Turquette , Emma Anholt , Stephen Boyd , Ray Jui , Scott Branden , Broadcom internal kernel review list , Daniel Vetter , David Airlie , Maxime Ripard Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Maxime Ripard , Stefan Wahren , linux-clk@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, Dom Cobley , dri-devel@lists.freedesktop.org X-Mailer: b4 0.11.0-dev-7da52 X-Developer-Signature: v=1; a=openpgp-sha256; l=3452; i=maxime@cerno.tech; h=from:subject:message-id; bh=oHROItAGNywnvJYBrN7pZtlhRHDQIJa7w2WOAz0D1No=; b=owGbwMvMwCX2+D1vfrpE4FHG02pJDMnu15b47m09yaP5K5Pvd6jdX/9WDWE1a8vTz+ZrydYvtHKR 1vzTUcrCIMbFICumyBIjbL4k7tSs151sfPNg5rAygQxh4OIUgIkkTGD4Zxxv+20F63LB8/+z+vbPmd Znq9ZUNN9CJvwYXyabcIY6EyPDqQsxJwUXNNhcs1CY7m0jFjy1QuK/jL9upbKxSFKU8F1GAA== X-Developer-Key: i=maxime@cerno.tech; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dom Cobley At least the 4096x2160@60Hz mode requires some overclocking that isn't available by default, even if hdmi_enable_4kp60 is enabled. Let's add some logic to detect whether we can satisfy the core clock requirements for that mode, and prevent it from being used otherwise. Signed-off-by: Dom Cobley Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_drv.h | 6 ++++++ drivers/gpu/drm/vc4/vc4_hdmi.c | 11 +++++++++-- drivers/gpu/drm/vc4/vc4_hvs.c | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 09cdbdb7fff0..094ebe8567e2 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -349,6 +349,12 @@ struct vc4_hvs { * available. */ bool vc5_hdmi_enable_scrambling; + + /* + * 4096x2160@60 requires a core overclock to work, so register + * whether that is sufficient. + */ + bool vc5_hdmi_enable_4096by2160; }; struct vc4_plane { diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index f367f93ca832..cf1fee6c29f3 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -1476,6 +1476,7 @@ vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, static enum drm_mode_status vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, + const struct drm_display_mode *mode, unsigned long long clock) { const struct drm_connector *connector = &vc4_hdmi->connector; @@ -1488,6 +1489,12 @@ vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, if (!vc4->hvs->vc5_hdmi_enable_scrambling && clock > HDMI_14_MAX_TMDS_CLK) return MODE_CLOCK_HIGH; + /* 4096x2160@60 is not reliable without overclocking core */ + if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && + mode->hdisplay > 3840 && mode->vdisplay >= 2160 && + drm_mode_vrefresh(mode) >= 50) + return MODE_CLOCK_HIGH; + if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) return MODE_CLOCK_HIGH; @@ -1522,7 +1529,7 @@ vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, unsigned long long clock; clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); - if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK) + if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) return -EINVAL; vc4_state->tmds_char_rate = clock; @@ -1685,7 +1692,7 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, (mode->hsync_end % 2) || (mode->htotal % 2))) return MODE_H_ILLEGAL; - return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); + return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); } static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index e28a13a75ec2..32f5ab937ace 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -698,6 +698,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) if (max_rate >= 550000000) hvs->vc5_hdmi_enable_scrambling = true; + if (max_rate >= 600000000) + hvs->vc5_hdmi_enable_4096by2160 = true; + hvs->max_core_rate = max_rate; ret = clk_prepare_enable(hvs->core_clk); -- b4 0.11.0-dev-7da52