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Date:   Thu, 13 Oct 2022 14:11:39 +0200
From:   Wolfram Sang <wsa+renesas@sang-engineering.com>
To:     Geert Uytterhoeven <geert+renesas@glider.be>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Sergei Shtylyov <sergei.shtylyov@gmail.com>,
        linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] memory: renesas-rpc-if: Add support for R-Car Gen4
Message-ID: <Y0gAezsj7gCAvL3U@shikoro>
Mail-Followup-To: Wolfram Sang <wsa+renesas@sang-engineering.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Sergei Shtylyov <sergei.shtylyov@gmail.com>,
        linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
References: <cover.1665583089.git.geert+renesas@glider.be>
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On Wed, Oct 12, 2022 at 04:01:52PM +0200, Geert Uytterhoeven wrote:
> The SPI Multi I/O Bus Controller (RPC-IF) on R-Car Gen4 SoCs is very
> similar to the RPC-IF on R-Car Gen3 SoCs.  It does support four instead
> of three bits of strobe timing adjustment (STRTIM), and thus requires a
> new mask and new settings.
>=20
> Inspired by a patch in the BSP by Cong Dang.
>=20
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

> +#define RPCIF_PHYCNT_STRTIM(v)	(((v) & 0x7) << 15 | ((v) & 0x8) << 24) /=
* valid for R-Car and RZ/G2{E,H,M,N} */

Very minor but I spent a minute to get it: To make sure the reader
easily understands that we want to set bit 27, we could make that maybe
more clear with:

	... | !!((v) & 0x8) << 27)

But if you prefer, we can keep it like this.


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