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Date:   Thu, 13 Oct 2022 15:24:30 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Harini Katakam <harini.katakam@amd.com>
Cc:     hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net,
        edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        harinikatakamlinux@gmail.com, michal.simek@amd.com,
        radhey.shyam.pandey@amd.com
Subject: Re: [PATCH] net: phy: dp83867: Extend RX strap quirk for SGMII mode
Message-ID: <Y0gRjoOOJQmGQ6Ao@lunn.ch>
References: <20221013072833.28558-1-harini.katakam@amd.com>
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In-Reply-To: <20221013072833.28558-1-harini.katakam@amd.com>
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On Thu, Oct 13, 2022 at 12:58:33PM +0530, Harini Katakam wrote:
> When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
> register should be set. The former is already handled in
> dp83867_config_init; add the latter in SGMII specific initialization.
> 
> Signed-off-by: Harini Katakam <harini.katakam@amd.com>
> ---
>  drivers/net/phy/dp83867.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index 6939563d3b7c..a2aac9032af6 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -853,6 +853,13 @@ static int dp83867_config_init(struct phy_device *phydev)
>  		else
>  			val &= ~DP83867_SGMII_TYPE;
>  		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
> +		/* This is a SW workaround for link instability if RX_CTRL is
> +		 * not strapped to mode 3 or 4 in HW. This is required for SGMII
> +		 * in addition to clearing bit 7, handled above.
> +		 */

Blank line before a comment please.

Should this have a fixes tag? Are there deployed boards which are
broken because of this? Or do you have a new board, using SGMII, which
is not deployed yet?

	 Andrew